XR16C2550 Datasheet, PDF (37/38 Pages) Exar Corporation – 2.97V TO 5.5V DUART WITH 16-BYTE FIFO

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2.97V TO 5.5V DUART WITH 16-BYTE FIFO
XR16C2550
REV. 1.0.0
5.0 TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
APPLICATIONS ............................................................................................................................................... 1
FEATURES ..................................................................................................................................................... 1
FIGURE 1. XR16C2550 BLOCK DIAGRAM......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT ..................................................................................................................................................... 2
ORDERING INFORMATION ................................................................................................................................ 2
PIN DESCRIPTIONS ......................................................................................................... 3
1.0 PRODUCT DESCRIPTION .................................................................................................................... 6
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 7
2.1 CPU INTERFACE ............................................................................................................................................. 7
FIGURE 3. XR16C2550 DATA BUS INTERCONNECTIONS ................................................................................................................. 7
2.2 DEVICE RESET ................................................................................................................................................ 7
2.3 CHANNEL A AND B SELECTION ................................................................................................................... 7
TABLE 1: CHANNEL A AND B SELECT ............................................................................................................................................... 7
2.4 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................ 8
2.5 DMA MODE ...................................................................................................................................................... 8
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE............................................................................................. 8
2.6 INTA AND INTB OUTPUTS .............................................................................................................................. 8
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER ........................................................................................................ 8
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER ............................................................................................................... 8
2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ............................................................................. 9
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS................................................................................................................................. 9
2.8 PROGRAMMABLE BAUD RATE GENERATOR ............................................................................................. 9
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE .......................................................................................... 10
FIGURE 6. OPERATING FREQUENCY VERSUS POWER SUPPLY CHART. ............................................................................................. 10
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ...................................................................... 11
2.9 TRANSMITTER ............................................................................................................................................... 11
2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY......................................................................................... 11
2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. 11
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 12
2.9.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 12
FIGURE 8. TRANSMITTER OPERATION IN FIFO MODE...................................................................................................................... 12
2.10 RECEIVER .................................................................................................................................................... 12
2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 13
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................... 13
FIGURE 10. RECEIVER OPERATION IN FIFO MODE ......................................................................................................................... 13
2.11 INTERNAL LOOPBACK ............................................................................................................................... 14
FIGURE 11. INTERNAL LOOP BACK IN CHANNEL A AND B ................................................................................................................ 14
3.0 UART INTERNAL REGISTERS ........................................................................................................... 15
TABLE 6: UART CHANNEL A AND B UART INTERNAL REGISTERS ..................................................................................... 15
TABLE 7: INTERNAL REGISTERS DESCRIPTION ................................................................................................................... 16
4.0 INTERNAL REGISTER DESCRIPTIONS ............................................................................................ 16
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 16
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 16
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ............................................................................. 16
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 17
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 17
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 18
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 18
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 18
TABLE 8: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 18
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ..................................................................................... 19
TABLE 9: RECEIVE FIFO TRIGGER LEVEL SELECTION ..................................................................................................................... 19
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ..................................................................................... 19
TABLE 10: PARITY SELECTION ........................................................................................................................................................ 21
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 21
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 22
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 23
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 24
4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 24
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