XR16C2550 Datasheet, PDF (18/38 Pages) Exar Corporation – 2.97V TO 5.5V DUART WITH 16-BYTE FIFO

XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
xr
REV. 1.0.1
4.4 Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 8, shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1 Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by a 4-char plus 12 bits delay timer.
• TXRDY is by TX FIFO empty.
• MSR is by any of the MSR bits 0, 1, 2 and 3.
4.4.2 Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register.
• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
• RXRDY Time-out interrupt is cleared by reading RHR.
• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
• MSR interrupt is cleared by a read to the MSR register.
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TABLE 8: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY LEVEL
ISR REGISTER STATUS BITS
BIT-3 BIT-2 BIT-1
BIT-0
SOURCE OF INTERRUPT
1
0
1
1
0 LSR (Receiver Line Status Register)
2
1
1
0
0 RXRDY (Receive Data Time-out)
3
0
1
0
0 RXRDY (Received Data Ready)
4
0
0
1
0 TXRDY (Transmit Ready)
5
0
0
0
0 MSR (Modem Status Register)
-
0
0
0
1 None (default)
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
• Logic 1 = No interrupt pending (default).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Table 8).
ISR[5:4]: Reserved
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
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