XR16L570 Datasheet, PDF (30/46 Pages) Exar Corporation – SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE

XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
xr
REV. 1.0.0
MSR[5]: DSR Input Status
Normally MSR bit-5 is the complement of the DSR# input in the 32-QFN package. In internal loopback mode,
this bit is equivalent to the DTR# bit (MCR[0]). The 24-QFN package of the L570 does not have the DSR#
modem input.
MSR[6]: RI Input Status
Normally MSR bit-6 is the complement of the RI# input in the 32-QFN package. In internal loopback mode, this
bit is equivalent to the OP1# bit (MCR[2]). The 24-QFN package of the L570 does not have the RI# modem
input.
MSR[7]: CD Input Status
Normally MSR bit-5 is the complement of the CD# input in the 32-QFN package. In internal loopback mode,
this bit is equivalent to the OP2# bit (MCR[3]). The 24-QFN package of the L570 does not have the CD#
modem input.
4.11 Scratchpad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.12 Baud Rate Generator Registers (DLL and DLM) - Read/Write
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
• Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
4.13 Device Identification Register (DVID) - Read Only
This register contains the device ID (0x01 for XR16L570). Prior to reading this register, DLL and DLM should
be set to 0x00.
4.14 Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
4.15 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 10). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
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