XR16L570 Datasheet, PDF (3/46 Pages) Exar Corporation – SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE

xr
REV. 1.0.0
XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
PIN DESCRIPTIONS
Pin Descriptions
24-QFN 32-QFN
NAME
TYPE
PIN# PIN#
DESCRIPTION
DATA BUS INTERFACE
A2
12
17
A1
13
18
A0
14
19
D7
3
5
D6
2
4
D5
1
3
D4
24
1
D3
23
32
D2
22
31
D1
21
30
D0
20
29
IOR#
11
14
IOW#
9
12
CS#
6
8
INT
15
20
I _{Address data lines [2:0]. These 3 address lines select one of the internal registers in}
the UART during a data bus transaction.
I/O _{Data bus lines [7:0] (bidirectional).}
I _{This input is the read strobe (active low). The falling edge instigates an internal read}
cycle and retrieves the data byte from an internal register pointed by the address
lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it
on the rising edge.
I _{This input is the write strobe (active low). The falling edge instigates the internal write}
cycle and the rising edge transfers the data byte on the data bus to an internal regis-
ter pointed by the address lines.
I _{This input is chip select (active low) to enable the device.}
O _{This output is the active high device interrupt output. The output state is defined by}
the user through the software setting of MCR[3]. INT is set to the active mode when
MCR[3] is set to a logic 1. INT is set to the three state mode when MCR[3] is set to a
logic 0. See MCR[3].
MODEM OR SERIAL I/O INTERFACE
TX
5
7
O _{UART Transmit Data or infrared encoder data. Standard transmit and receive inter-}
face is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic 1 during
reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when
MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it unconnected.
RX
4
6
I _{UART Receive Data or infrared receive data. Normal receive data input must idle at}
logic 1 condition. The infrared receiver idles at logic 0.
RTS# 16
21
O _{UART Request-to-Send (active low) or general purpose output. This output must be}
asserted prior to using auto RTS flow control, see EFR[6], MCR[1] and IER[6].
CTS# 18
24
I _{UART Clear-to-Send (active low) or general purpose input. It can be used for auto}
CTS flow control, see EFR[7], MSR[4] and IER[7]. This input should be connected to
VCC when not used.
DTR#
-
22
O _{UART Data-Terminal-Ready (active low) or general purpose output. This pin is not}
available in the 24-QFN package.
DSR#
-
25
I _{UART Data-Set-Ready (active low) or general purpose input. This input should be}
connected to VCC when not used. This input has no effect on the UART. This pin is
not available in the 24-QFN package.
3