XR16L570 Datasheet, PDF (20/46 Pages) Exar Corporation – SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE

XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
xr
REV. 1.0.0
.
TABLE 6: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
001
IER RD/WR 0/
0/
0/
0/
Modem RX Line TX
RX
Stat. Int. Stat. Empty Data ^LCR[7]=0
CTS Int. RTS Int. Xoff Int. Sleep _{Enable Int.}
Int
Int.
Enable Enable Enable Mode
Enable Enable Enable
Enable
010
010
ISR
FCR
RD FIFOs FIFOs
0/
0/
INT
INT INT INT
Enabled Enabled
INT
INT
Source Source
Source Source Source Source
Bit-3 Bit-2 Bit-1 Bit-0
Bit-5 Bit-4
LCR ≠ 0xBF
WR RXFIFO RXFIFO 0/
0/
DMA
TX
RX FIFOs
Trigger Trigger
TXFIFO TXFIFO
Trigger Trigger
Mode
Enable
FIFO FIFO Enable
Reset Reset
011
LCR RD/WR Divisor Set TX Set Par- Even
Enable Break
ity
Parity
Parity
Enable
Stop
Bits
Word Word
Length Length
Bit-1 Bit-0
100
101
110
111
000
001
000
001
MCR RD/WR
0/
BRG
Pres-
caler
0/
IR Mode
ENable
0/
XonAny
Internal
Loop-
back
Enable
INT Out-
put
Enable
(OP2#)
(OP1#) RTS# DTR#
Output Output
Invert _{Control Control}
IR RX
LSR RD RX FIFO THR & THR
RX RX Fram- RX
RX
RX _{LCR ≠ 0xBF}
Global TSR Empty Break ing Error Parity Over- Data
Error Empty
Error run Ready
Error
MSR RD
CD#
Input
RI#
Input
DSR# CTS#
Input Input
Delta
CD#
Delta Delta Delta
RI# DSR# CTS#
SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0 LCR ≠ 0xBF
DLL RD/WR Bit-7
Baud Rate Generator Divisor
Bit-6 Bit-5 Bit-4
Bit-3
Bit-2 Bit-1 Bit-0 ^LCR[7]=1
DLM RD/WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
DREV RD
DVID RD
Bit-7
0
Bit-6
0
Bit-5
0
Bit-4
0
Bit-3
0
Bit-2
0
Bit-1
0
Bit-0
1
LCR[7]=1
DLL=0x00
DLM=0x00
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