XRD9814B Datasheet, PDF (18/53 Pages) Exar Corporation – 3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors

XRD9814B/9816B
(Correlated Double Sampling)
Correlated double sampling is a technique used to level
shift and acquire CCD output signals whose informa-
tion is equal to the difference between consecutive
reference (black) and signal (video) samples. The CDS
process consists of three steps:
1) Sampling and holding the reference black level.
2) Sampling the video level.
3) Subtracting the two samples to extract the video
information.
Once the video information has been extracted it can
be processed further through amplification and/or off-
set adjustment. Since system noise is also stored and
subtracted during the CDS process, signals with band-
widths less than half the sampling frequency will be
substantially attenuated.
In order to reject higher frequency power supply noise
which is not attenuated near the sampling frequency
the XRD9814B/9816B utilizes a fully differential input
structure.
Since the CDS process uses AC coupled inputs the
coupling capacitor must be charged to the common-
mode range of the analog front-end. This can be
accomplished by clamping the coupling capacitor to
the internal clamp voltage when the CCD is at a
reference level. This clamp may occur during each
pixel (Pixel Clamp), or at the beginning of each line
(CDS Line Clamp). If CDS Line Clamp mode is used the
input buffer (configuration register #1, PB1) must be
enabled to eliminate the effects of input bias current.
If Pixel mode is selected the input buffer is not required
or recommended.
3-Channel CDS Mode
This mode allows simultaneous CDS of the red, green
and blue inputs . Black-level sampling occurs on each
pixel and is equal to the width of the BSAMP sampling
input. The black level is held on the falling edge of
BSAMP and the PGA will immediately begin to track
the signal input until the falling edge of VSAMP.
Two VSAMP timing modes are supported to allow
additional flexibility in the VSAMP pulse width (see
timing diagrams). At the end of the video sampling
phase the difference between the reference and video
levels is inverted, amplified and offset depending on
the contents of the PGA gain and offset registers. The
RGB channels are then sequentially converted by a
high speed A/D converter. A/D converter data appears
on the data output bus after 7 ADCCLK cycles. The
green channel is synchronized on the rising edge of the
first ADCCLK after the falling edge of VSAMP. The
power-up default mode is for CDS sampling a CCD
input (Pixel Clamp, Inverting Input, No Input Buffer).
1-Channel CDS Mode
The 1-Channel CDS mode allows high-speed acquisi-
tion and processing of a single channel. The timing,
clamp and buffer configurations are similar to the 3-
channel mode described previously. To select a single
channel input the color bits of configuration register 1
must be set to the appropriate value. The A/D input will
begin to track the selected color input on the next
positive edge of ADCCLK. If the configuration is
toggled from single color to 3-channel mode RGB
scanning will not occur until the circuit is
resynchronized on the falling edge of VSAMP.
Rev. 1.00
18