XRD9814B Datasheet, PDF (16/53 Pages) Exar Corporation – 3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors

XRD9814B/9816B
VSAMP Timing
Reading Register Data
This allows the user to select one of two VSAMP timing
controls. Timing Option #2 allows the rising edge of
VSAMP to occur approximately one-half ADCCLK
earlier than Option #1. This does not affect internal
timing and is provided only to allow additional flexibility
in the external timing control. Timing Option #2 is
available only in the 3-channel mode of operation (See
timing diagrams Figure 3 and Figure 4).
Configuration Register #2
The bit assignment and definition for this register is
detailed in the Configuration Register #2 Definition
Table. A diagnostic read-back mode allows gain,
offset and configuration data to be output as the 8 or 10
MSBs on the digital output bus depending on the
selection of OUTSEL (see Reading Register Data
session for details). Additional bits are used to enable
a low-power stand-by state and manufacturing test
mode.
Digital Reset
Setting this bit to one resets all registers to all zeros.
In order to enter read-back mode, set configuration
register #2, PB0 to 1. Follow the write timing in Figures
17 and 18.
In order to read a specific register, shift in 3-bits of
register address data (MSB first), followed by 10
dummy data bits. In the case of reading back configu-
ration register #2, PB0 has to stay 1 and cannot be a
dummy.
Read-Back Registers and Address
Address Data
001 XXXXXXXXXX
001 XXXXXXXXX1
010 XXXXXXXXXX
011 XXXXXXXXXX
100 XXXXXXXXXX
101 XXXXXXXXXX
110 XXXXXXXXXX
111 XXXXXXXXXX
Register
Cfig1
Cfig2
Red Gain
Grn Gain
Blu Gain
Red Offset
Grn Offset
Blu Offset
In order to exit read-back mode perform a write to
configuration register 2, PB0=0.
Test Mode
This is a reserved bit for testing and must be set to 0
in all writes to Configuration Register #2.
Stand-By Mode
Setting this bit to one forces the circuit into a low-power
standby mode. Configuration, offset and gain registers
remain unchanged in stand-by mode. Pull OEB High
to set DB<15:0> to high impedance during stand-by
mode.
(OUTSEL = 0) In read-back mode the A/D output is
bypassed and internal register data is output to the 10
most significant bits of the data output bus. The
remaining LSB bits should be ignored. Register data
will be valid after the load pin goes high.
(OUTSEL = 1) In nibble mode, the output bus is limited
to 8-bits. Therefore, in read-back mode, the 8 MSBs
are valid when ADCCLK is high, and the 2 LSBs are
valid when ADCCLK is low. Configuring and exiting the
read-back mode is done in the same manner of
OUTSEL = 0.
Read Back Mode
This is a special diagnostic mode which can aid in the
debugging of new system designs. Setting this bit to 1
allows all configuration, gain and offset register con-
tents to be output on the data output bus (explained
below).
Important: The entire byte of register #2 is re-written when
exiting the readback mode. If any bits of configuration
register #2 were programmed prior to entering the read-
back mode, they must be re-programmed when exiting
read-back. See Figure 19 for read-back timing.
PGA Gain Settings
Rev. 1.00
The gain for each color input is individually program-
mable from 1 to 10 in 1024 linear steps.
16