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XRD9814B Datasheet, PDF (17/53 Pages) Exar Corporation – 3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors
XRD9814B/9816B
PGA
Gain
=

Code
1024

⋅
9.0
+
1
where Code represents the binary contents of the 10-
bit gain setting register.
Channel Offset Adjustment
The gross offset correction for each channel is
progammable from -400mV to +200mV. It is adjusted
by toggling PB9 and PB8 of Offset Registers (Table 4).
The fine offset correction for each channel is program-
mable from -300mV to +300mV.
Fine Channel Offset =
PB 7 ⋅


( Code ) 
128 
⋅
300mV
PB7=1 equals -1
PB7=0 equals +1
Code = (PB6:PB0) of the 10-bit offset register.
Differential
Input
Offset Block
CDS
10-Bit
PGA
8-Bit Offset DAC
Fine Adjust
XRD9814B/16B
Vout
2-Bit Offset
Variable Capacitive Divider
Gross Adjust
3:1
MUX
14-Bit
ADC
Block Diagram of the Fine and Gross Offset Adjustment DAC
Theory ofROepv.er1a.t0i0on
17