XRD9814B Datasheet, PDF (15/53 Pages) Exar Corporation – 3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors

XRD9814B/9816B
No-Clamp Mode (S/H with DC input)
Used for DC coupled inputs. AC coupled inputs must
be externally clamped to the proper common-mode
input voltage of the XRD9814B/9816B.
Note: Pixel clamp is the default clamp mode.
Clamp PB7 PB6 Clamp Enable
Mode
Pixel
0
0 BSAMP
CDS Line 0
1 BSAMP LCLMP
No Clamp 1
0 Disabled
S/H Line 1
1 LCLMP
Table 5. Clamp Enable Definition
BSAMP
LCLMP
PB6
PB7
Clamp
Enable
Figure 2. Clamp Enable Logic
A/D Full-Scale Range
This bit sets the Full-Scale Range (FSR) of the A/D
converter to 2V or 3V. Use the 3V FSR for lowest
noise performance.
Color Select
The color input corresponds to the signal input to be
digitized by the A/D converter. If set to RGB (default)
the A/D input is sequentially cycled through the red,
green and blue channels. The green channel is syn-
chronized on the rising edge of the first ADCCLK after
the falling edge of VSAMP. If set in single-channel mode,
the A/D multiplexer will not sequence and the A/D con-
verter input will be continually connected to the chan-
nel that is selected, RED, GRN or BLU.
Signal Polarity
This bit configures the analog inputs for positive or
negative transitioning inputs. This is required to pro-
vide the correct signal polarity to the A/D input and to
set the correct input clamp level. The default configu-
ration is set to inverting mode (CCD input).
Input Buffer Enable
This bit enables the input buffer to the PGA amplifier
and is required only for AC coupled inputs operating in
CDS line or S/H line clamp modes. Since this input
buffer reduces the input voltage range its use is not
recommended under DC or pixel-mode operation. The
input buffer is disabled in the default configuration.
Rev. 1.00
15