SLU08G72K1BD2SA-CCRT Datasheet, PDF (8/16 Pages) List of Unclassifed Manufacturers – 8192MB DDR3L – SDRAM ECC DIMM

Data Sheet
Rev.1.0 17.02.2014
Parameter
& Test Condition
max.
Symbol
Unit
12800 CL11 10600 CL9
OPERATING WRITE CURRENT:
All device banks open, Continuous burst writes; One
I_DD4W
module rank active; BL = 4, CL = CL (I_DD), AL = 0;
t_CK = t_CK (I_DD), t_RAS = t_RAS MAX (I_DD), t_RP = t_RP (I_DD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are changing once every two clock
cycles; DQ inputs changing once per clock cycle
BURST REFRESH CURRENT:
I_DD5
t_CK = t_CK (I_DD); refresh command at every t_RFC (I_DD) interval,
CKE is HIGH, CS# is HIGH between valid commands; All
other Control and Address bus inputs are changing once
every two clock cycles; DQ inputs changing once per
clock cycle
SELF REFRESH CURRENT:
I_DD6
CK and CK# at 0V; CKE ≤ 0.2V; All other Control and
Address bus inputs are floating at V_REF; DQ’s are floating
at V_REF
OPERATING CURRENT*) :
I_DD7
Four device bank interleaving READs, I_OUT = 0mA; BL = 4, CL
= CL (I_DD), AL = t_RCD (I_DD) – 1 x t_CK (I_DD); t_CK = t_CK (I_DD), t_RC
= t_RC (I_DD), t_RRD = t_RRD (I_DD), t_RCD = t_RCD (I_DD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are not changing during DESELECT;
DQ inputs changing once per clock cycle
684
603
mA
1782
1782
mA
216
216
mA
1206
1179
mA
*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)
mode.
TIMING VALUES USED FOR I_DD MEASUREMENT
IDD MEASUREMENT CONDITIONS
SYMBOL
12800 CL11 10600 CL9
CL (IDD)
11
9
t_RCD (IDD)
t_RC (IDD)
t_RRD (IDD)
t_CK (IDD)
13.75
13.5
48.75
49.5
6.25
6
1.25
1.5
t_RAS MIN (IDD)
t_RAS MAX (IDD)
35
70’200
36
70’200
t_RP (IDD)
t_RFC (IDD)
13.75
13.5
260
260
Unit
t_CK
ns
ns
ns
ns
ns
ns
ns
t_CK
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
Page 8
of 16