SLU08G72K1BD2SA-CCRT Datasheet, PDF (2/16 Pages) List of Unclassifed Manufacturers – 8192MB DDR3L – SDRAM ECC DIMM

Data Sheet
Rev.1.0 17.02.2014
This Swissbit module is an industry standard 240-pin 8-byte DDR3 SDRAM Dual-In-line Memory Module
(UDIMM) which is organized as x72 high speed CMOS memory arrays. The module uses internally configured
octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-speed
operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses
to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_15 compatible.
The module can operate either at DDR3 mode (1.50V VDD) or DDR3L mode (1.35V VDD)
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and several
timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
1G x 72bit
DDR3 SDRAMs used
18 x 512M x 8bit (4Gbit)
Row
Addr.
16
Device Bank
Addr.
BA0, BA1, BA2
Column
Addr.
10
Refresh
Module
Bank Select
8k
S0#, S1#
Module Dimensions
in mm
133.35 (long) x 18.75 (high) x 4.00 [max] (thickness)
Timing Parameters
Part Number
SLU08G72K1BD2SA-CCRT
SLU08G72K1BD2SA-DCRT
Module Density
8GByte
8GByte
Transfer Rate
10.6 GB/s
12.8 GB/s
Clock Cycle/Data bit rate
1.5ns/1333MT/s
1.25ns/1600MT/s
Latency
9-9-9
11-11-11
Pin Name
A0 – A9, A11 – A15
A10/AP
A12/BC#
BA0 – BA2
DQ0 – DQ63
CB0 – CB7
DM0 – DM8
DQS0 – DQS8
DQS0# - DQS8#
RAS#
CAS#
WE#
CKE0 – CKE1
S0#, S1#
CK0 – CK1
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Address Inputs
Address Input / Autoprecharge Bit
Address Input / Burst chop
Bank Address Inputs
Data Input / Output
ECC check bits
Input Data Mask
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Chip Select
Clock inputs, positive line
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
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