SLU08G72K1BD2SA-CCRT Datasheet, PDF (1/16 Pages) List of Unclassifed Manufacturers – 8192MB DDR3L – SDRAM ECC DIMM

Data Sheet
Rev.1.0 17.02.2014
8192MB DDR3L – SDRAM ECC DIMM
240 Pin unbuffered ECC DIMM
SLU08G72K1BD2SA-xxRT
8GByte in FBGA Technology
RoHS compliant
Options:
 Data Rate / Latency
DDR3 1333 MT/s CL9
DDR3 1600 MT/s CL11
Marking
-CC
-DC
 Module Density
8GByte with 18 dies and 2 ranks
 Standard Grade
E-Grade
W-Grade
(T_A) 0°C to 70°C
(T_C) 0°C to 85°C
(T_A) 0°C to 85°C
(T_C) 0°C to 95°C *)
(T_A) -40°C to 85°C
(T_C) -40°C to 95°C *)
The refresh rate has to be doubled when 85°C<TC<95°C
Environmental Requirements:
 Operating temperature (ambient)
Standard Grade
0°C to 70°C
E-Grade
0°C to 85°C
W-Grade
-40°C to 85°C
 Operating Humidity
10% to 90% relative humidity, noncondensing
 Operating Pressure
105 to 69 kPa (up to 10000 ft.)
 Storage Temperature
-55°C to 100°C
 Storage Humidity
5% to 95% relative humidity, noncondensing
 Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Features:
 240-pin 72-bit DDR3 Dual-In-Line Double Data Rate
Synchronous DRAM module with ECC
 Module organization: dual rank 1G x 72
 VDD = 1.35V and 1.5V
 VDDQ = 1.35V and 1.5V
 1.5V I/O ( SSTL_15 compatible)
 Supports ECC, error detection and correction
 On-board I²C temperature sensor with integrated serial
presence-detect (SPD) EEPROM
(according to JEDEC JESD21C)
 Finish Process: OSP with 30µ” AU on contact fingers
 This module is fully pin and functional compatible to the
JEDEC PC3-12800 spec. and JEDEC- Standard MO-269.
(see www.jedec.org)
 The pcb and all components are manufactured according
to the RoHS compliance specification [EU Directive
2002/95/EC Restriction of Hazardous Substances (RoHS)]
 DDR3L - SDRAM component Samsung K4B4G0846D
 512Mx8 DDR3 SDRAM in PG-TFBGA-78 package
 8-bit pre-fetch architecture
 Programmable CAS Latency, CAS Write Latency, Additive
Latency, Burst Length and Burst Type.
 On-Die-Termination (ODT) and Dynamic ODT for improved
signal integrity.
 Refresh. Self Refresh and Power Down Modes.
 ZQ Calibration for output driver and ODT.
 System Level Timing Calibration Support via Write Leveling
and Multi Purpose Register (MPR) Read Pattern.
Figure: mechanical dimensions¹
1_{if no tolerances specified ± 0.15mm}
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
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