SLU08G72K1BD2SA-CCRT Datasheet, PDF (6/16 Pages) List of Unclassifed Manufacturers – 8192MB DDR3L – SDRAM ECC DIMM

Data Sheet
Rev.1.0 17.02.2014
MAXIMUM ELECTRICAL DC CHARACTERISTICS
PARAMETER/ CONDITION
V_DD Supply Voltage relative to V_SS
I/O V_DD Supply Voltage relative to V_SS
Voltage on any pin relative to V_SS
INPUT LEAKAGE CURRENT
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V
(All other pins not under test = 0V)
SYMBOL
V_DD
V_DDQ
V_IN, V_OUT
I_I
Command/Address
RAS#, CAS#, WE#, S#, CKE
CK, CK#
DM
OUTPUT LEAKAGE CURRENT
I_OZ
(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ)
DQ, DQS, DQS#
V_REF LEAKAGE CURRENT ; V_REF is on a valid level
I_VREF
MIN
-0.4
-0.4
-0.4
-16
-16
-2
-5
-8
MAX
1.975
1.975
1.975
16
16
2
5
UNITS
V
V
V
µA
µA
8
µA
DDR3L (1.35V) DC OPERATING CONDITIONS
PARAMETER/ CONDITION
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
SYMBOL
SYMBOL
V_DD
V_DDQ
V_REF
V_TT
V_{IH (DC90)}
MIN
MIN
1.283
1.283
0.49 x V_DDQ
0.49 x V_DDQ-20mV
V_REF + 90mV
NOM
NOM
1.35
1.35
0.50 x V_DDQ
0.50 x V_DDQ
MAX
MAX
1.450
1.450
0.51x V_DDQ
0.51x V_DDQ+20mV
V_DDQ + 0.3
UNITS
UNITS
V
V
V
V
V
DDR3 (1.50V) DC OPERATING CONDITIONS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
V_DD
V_DDQ
V_REF
V_TT
V_{IH (DC)}
V_{IL (DC)}
MIN
1.425
1.425
0.49 x V_DDQ
0.49 x V_DDQ-20mV
V_REF + 0.1
-0.3
NOM
1.5
1.5
0.50 x V_DDQ
0.50 x V_DDQ
MAX
1.575
1.575
0.51x V_DDQ
0.51x V_DDQ+20mV
V_DDQ + 0.3
V_REF – 0.1
UNITS
V
V
V
V
V
V
AC INPUT OPERATING CONDITIONS
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
V_{IH (AC)}
V_{IL (AC)}
MIN
V_REF + 0.175
-
MAX
-
V_REF - 0.175
UNITS
V
V
CAPACITANCE
At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values.
When inductance and delay parameters associated with trace lengths are used in simulations, they are
significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then
render a considerably more accurate result. JEDEC modules are now designed by using simulations to close
timing budgets.
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
Page 6
of 16