W77L32 Datasheet, PDF (69/76 Pages) Winbond – 8-BIT MICROCONTROLLER

W77L32/W77L032A/W77M032A
14.2.1 MOVX Characteristics Using Strech Memory Cycles
PARAMETER
SYM.
VARIABLE
CLOCK
MIN.
VARIABLE
CLOCK
MAX.
UNITS STRECH
Data Access ALE Pulse Width
t_LLHL2
1.5 tCLCL - 5
2.0 tCLCL - 5
nS
tMCS = 0
tMCS > 0
Address Hold After ALE Low for
MOVX Write
t_LLAX2
0.5 tCLCL - 5
nS
RD Pulse Width
WR Pulse Width
RD Low to Valid Data In
t_RLRH
2.0 tCLCL - 5
tMCS - 10
nS
tMCS = 0
tMCS > 0
t_WLWH
2.0 tCLCL - 5
tMCS - 10
nS
tMCS = 0
tMCS > 0
t_RLDV
2.0 tCLCL - 20
nS
tMCS = 0
tMCS - 20
tMCS > 0
Data Hold after Read
t_RHDX
0
nS
Data Float after Read
t_RHDZ
tCLCL - 5
nS
2.0 tCLCL - 5
ALE Low to Valid Data In
t_LLDV
2.5 tCLCL - 5
nS
tMCS + 2tCLCL - 40
Port 0 Address to Valid Data In
t_AVDV1
3.0 tCLCL - 20
nS
2.0tCLCL - 5
Port 2 Address to Valid Data In
t_AVDV2
3.5 tCLCL - 20
nS
2.5 tCLCL - 5
ALE Low to RD or WR Low
t_LLWL
0.5 tCLCL - 5
1.5 tCLCL - 5
0.5 tCLCL + 5
1.5 tCLCL + 5
nS
Port 0 Address to RD or WR Low
t_AVWL
tCLCL - 5
2.0 tCLCL - 5
nS
Port 2 Address to RD or WR Low
t_AVWL2
1.5 tCLCL - 5
2.5 tCLCL - 5
nS
-5
Data Valid to WR Transition
t_QVWX
1.0 tCLCL - 5
nS
Data Hold after Write
t_WHQX
tCLCL - 5
2.0 tCLCL - 5
nS
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
RD Low to Address Float
t_RLAZ
0.5 tCLCL - 5
nS
RD or WR High to ALE High
t_WHLH
0
1.0 tCLCL - 5
10
1.0 tCLCL + 5
nS
tMCS = 0
tMCS > 0
Note: tMCS is a time period related to the Stretch memory cycle selection. The following table shows the time period of tMCS for
each selection of the Stretch value.
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Publication Release Date: April 17, 2007
Revision A6