W77L32 Datasheet, PDF (45/76 Pages) Winbond – 8-BIT MICROCONTROLLER

W77L32/W77L032A/W77M032A
8.3 Power Down Mode
The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does this
will be the last instruction to be executed before the device goes into Power Down mode. In the Power
Down mode, all the clocks are stopped and the device comes to a halt. All activity is completely
stopped and the power consumption is reduced to the lowest possible value. In this state the ALE and
PSEN pins are pulled low. The port pins output the values held by their respective SFRs.
The W77L032 will exit the Power Down mode with a reset or by an external interrupt pin enabled as
either level or edge detect. An external reset can be used to exit the Power down state. The high on
RST pin terminates the Power Down mode, and restarts the clock. The program execution will restart
from 0000h. In the Power down mode, the clock is stopped, so the Watchdog timer cannot be used to
provide the reset to exit Power down mode.
The W77L032 can be woken from the Power Down mode by forcing an external interrupt pin activated,
provided the corresponding interrupt is enabled, while the global enable(EA) bit is set. If these
conditions are met, then the low level on the external pin re-starts the oscillator. Then device executes
the interrupt service routine for the corresponding external interrupt. After the interrupt service routine
is completed, the program execution returns to the instruction after the one which put the device into
Power Down mode and continues from there. When RGSL(EXIF.1) bit is set to 1, the CPU will use the
internal RC oscillator instead of crystal to exit Power Down mode. The microcontroller will automatically
switch from RC oscillator to crystal after clock is stable. The RC oscillator runs at approximately 2−4
MHz. Using RC oscillator to exit from Power Down mode saves the time for waiting crystal start-up. It is
useful in the low power system which usually be awakened from a short operation then returns to
Power Down mode.
Table 5. Status of external pins during Idle and Power Down
MODE
Idle
PROGRAM
MEMORY
Internal
ALE
1
PSEN
1
PORT0
Data
Idle
External
1
1
Float
Power Down
Internal
0
0
Data
Power Down
External
0
0
Float
PORT1
Data
Data
Data
Data
PORT2 PORT3
Data
Address
Data
Data
Data
Data
Data
Data
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Publication Release Date: April 17, 2007
Revision A6