N78E366A Datasheet, PDF (66/136 Pages) List of Unclassifed Manufacturers – Microcontroller

N78E366A Data Sheet
Master/Slave
MCU1
MISO
MOSI
SPCLK
SS
0
I/O 1
PORT 2
3
Master/Slave
MCU2
MISO
MOSI
SPCLK
SS
0
1 I/O
2 PORT
3
Slave device 1 Slave device 2 Slave device 3
Figure 14–2. SPI Multi-master, Multi-slave Interconnection
Figure 14–2 shows a typical interconnection of SPI devices. The bus generally connects devices together
through three signal wires, MOSI to MOSI, MISO to MISO, and SPCLK to SPCLK. The Master devices select
the individual Slave devices by using four pins of a parallel port to control the four SS pins. MCU1 and MCU2
play either Master or Slave mode. The SS should be configured as Master Mode Fault detection to avoid mul-
ti-master conflict.
SPI shift register
76543210
MOSI MOSI
MISO MISO
SPI shift register
76543210
SPCLK SPCLK
SPI clock
generator
Master MCU
SS
*
* SS configuration follows DISMODF and SSOE bits.
SS
VSS
Slave MCU
Figure 14–3. SPI Single-master, Single-slave Interconnection
Figure 14–3 shows the simplest SPI system interconnection, single-master and signal-slave. During a transfer,
the Master shifts data out to the Slave via MOSI line. While simultaneously, the Master shifts data in from the
Slave via MISO line. The two shift registers in the Master MCU and the Slave MCU can be considered as one
16-bit circular shift register. Therefore, while a transfer data pushed from Master into Slave, the data in Slave
will also be pulled in Master device respectively. The transfer effectively exchanges the data which was in the
SPI shift registers of the two MCUs.
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Publication Release Date: March 11, 2011
Revision: V2.0