N78E366A Datasheet, PDF (65/136 Pages) List of Unclassifed Manufacturers – Microcontroller

Figure 14–1 shows SPI block diagram. It provides an overview of SPI architecture in this device. The main
blocks of SPI are the SPI control register logic, SPI status logic, clock rate control logic, and pin control logic.
For a serial data transfer or receiving, The SPI block exists a shift register and a read data buffer. It is single
buffered in the transmit direction and double buffered in the receiving direction. Transmit data cannot be written
to the shifter until the previous transfer is complete. Receiving logic consists of parallel read data buffer so the
shift register is free to accept a second data, as the first received data will be transferred to the read data buff-
er.
The four pins of SPI interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock
(SPCLK), and Slave Select ( SS ). The MOSI pin is used to transfer a 8-bit data in series from the Master to the
Slave. Therefore, MOSI is an output pin for Master device and a input for Slave. Respectively, the MISO is
used to receive a serial data from the Slave to the Master.
The SPCLK pin is the clock output in Master mode, but is the clock input in Slave mode. The shift clock is used
to synchronize the data movement both in and out of the devices through their MOSI and MISO pins. The shift
clock is driven by the Master mode device for eight clock cycles which exchanges one byte data on the serial
lines. For the shift clock is always produced out of the Master device, the system should never exist more than
one device in Master mode for avoiding device conflict.
Each Slave peripheral is selected by one Slave Select pin ( SS ). The signal must stay low for any Slave ac-
cess. When SS is driven high, the Slave device will be inactivated. If the system is multi-slave, there should be
only one Slave device selected at the same time. In the Master mode MCU, the SS pin does not function and
it can be configured as a general purpose I/O. However, SS can be used as Master Mode Fault detection (see
Section 14.7 “Mode Fault Detection” on page 73) via software setting if multi-master environment exists.
N78E366A also provides auto-activating function to toggle SS between each byte-transfer.
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Publication Release Date: March 11, 2011
Revision: V2.0