N78E366A Datasheet, PDF (46/136 Pages) List of Unclassifed Manufacturers – Microcontroller

N78E366A Data Sheet
CONFIG3
7
CWDTEN
r/w
6
EN6T
r/w
5
ROG
r/w
4
CKF
r/w
3
INTOSCFS
r/w
2
1
0
-
FOSC
-
-
r/w
-
unprogrammed value: 1111 1111b
Bit
Name
Description
7
CWDTEN CONFIG Watchdog Timer enable.
1 = Disable Watchdog Timer after all resets.
0 = Enable Watchdog Timer after all resets.
WDCON – Watchdog Timer Control (TA protected)
7
6
5
4
3
2
1
0
WDTEN^[1] WDCLR
-
WIDPD^[2] WDTRF^[3]
WPS2^[2]
WPS1^[2]
WPS0^[2]
r/w
w
-
r/w
r/w
r/w
r/w
r/w
Address: AAH
reset value: see Table 6–2. N78E366A SFR Descriptions and Reset Values
Bit
Name
Description
7
WDTEN Watchdog Timer enable.
0 = Disable Watchdog Timer.
1 = Enable Watchdog Timer. The WDT counter starts running.
6
WDCLR Watchdog Timer clear.
Setting this bit will reset the Watchdog Timer count to 00H. It puts the counter in a
known state and prohibit the system from reset. Note that this bit is written-only
and has no need to be cleared via software.
5
-
Reserved.
4
WIDPD Watchdog Timer running in Idle and Power Down mode.
This bit decides whether Watchdog Timer runs in Idle or Power Down mode.
0 = WDT counter is halted while CPU is in Idle or Power Down mode.
1 = WDT keeps running while CPU is in Idle or Power Down mode.
3
WDTRF Watchdog Timer reset flag.
When the CPU is reset by Watchdog Timer time-out event, this bit will be set via
hardware. This flag is recommended to be cleared via software.
2
WPS2 Watchdog Timer clock pre-scalar select.
These bits determine the scale of the clock divider for WDT counter. The scale is
1
WPS1 _{from 1/1 through 1/256. See Table 11–1.}
0
WPS0
[1] WDTEN is initialized by the inversed value of CWDTEN (CONFIG3.7) after all resets.
[2] WIDPD and WPS[2:0] are cleared after power-on reset, and keep unchanged after any other resets.
[3] WDTRF will be cleared after power-on reset, be set after Watchdog Timer reset, and remains unchanged after any oth-
er resets.
The
Watchdog
time-out
interval
is
determined
by
the
formula
1
 64 .
F_LOSC  clock dividerscalar
where
F_ILRC
is
the frequency of internal 10kHz RC. The following table shows an example of the Watchdog time-out interval
under different F_WCK and pre-scalars.
- 46 -
Publication Release Date: March 11, 2011
Revision: V2.0