N78E366A Datasheet, PDF (108/136 Pages) List of Unclassifed Manufacturers – Microcontroller

N78E366A Data Sheet
WDCON – Watchdog Timer Control (TA protected)
7
6
5
4
3
2
1
0
WDTEN WDCLR
-
WIDPD
WDTRF
WPS2
WPS1
WPS0
r/w
w
-
r/w
r/w
r/w
r/w
r/w
Address: AAH
reset value: see Table 6–2. N78E366A SFR Descriptions and Reset Values
Bit
Name
Description
3
WDTRF Watchdog Timer reset flag.
When the CPU is reset by Watchdog Timer time-out event, this bit will be set via
hardware. This flag is recommended to be cleared via software.
22.1 Power-on Reset
N78E366A incorporate an internal voltage reference. During a power-on process of rising power supply voltage
V_DD, this voltage reference will hold the CPU in power-on reset mode when V_DD is lower than the voltage refer-
ence threshold. This design makes CPU not access program flash while the V_DD is not adequate performing
the flash reading. If a undetermined operating code is read from the program flash and executed, this will put
CPU and even the whole system in to a erroneous state. After a while, V_DD rises above the reference threshold
where the system can work, the selected oscillator will start and then program code will be executed from
0000H. At the same time, a power-on flag POF (PCON.4) will be set 1 to indicate a cold reset, a power-on re-
set complete. Note that the contents of internal RAM will be undetermined after a power-on. The user is rec-
ommended to give initial values for the RAM block.
The POF is recommended to be cleared to 0 via software in order to check if a cold reset or warm reset per-
formed after the next reset occurs. If a cold reset caused by power off and on, POF will be set 1 again. If the
reset is a warm reset caused by other reset sources, POF will remain 0. The user may take a different course
to check other reset flags and deal with the warm reset event.
22.2 Brown-out Reset
Brown-out detection circuit is for monitoring the V_DD level during execution. When V_DD drops to the selected
Brown-out trigger level (V_BOD), the Brown-out detection logic will reset the CPU if BORST (PMC.4) setting 1.
After a Brown-out reset, BORF (RSR.2) will set 1 via hardware. It will not be altered by any reset other than a
power-on reset. Software can clear this bit.
22.3 RST Pin Reset
The hardware reset input is RST pin which is the input with a Schmitt trigger. A hardware reset is accomplished
by holding the RST pin high for at least two machine-cycles to ensure detection of a valid hardware reset sig-
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Publication Release Date: March 11, 2011
Revision: V2.0