W79E632A Datasheet, PDF (63/79 Pages) Winbond – 8-BIT MICROCONTROLLER

W79E632A/W79L632A
16. SECURITY BITS
1. Using device programmer, the Flash EPROM can be programmed and verified repeatedly. Until the
code inside the Flash EPROM is confirmed OK, the code can be protected. The protection of Flash
EPROM and those operations on it are described below. The W79E(L)632 has Special Setting
Register which can be accessed by device programmer. The register can only be accessed from the
Flash EPROM operation mode. Those bits of the Security Registers can not be changed once they
have been programmed from high to low. They can only be reset through erase-all operation. If you
needn’t have ISP function, please don’t fill “FF” code on LD memory. The writer always writes AP and
LD flashs every time.
B7 B6 B5 B4 B3 B2 B1 B0 Security Bits
B7 : 1 -> XT > 24M hz, 0: XT < 24M hz.
B5 : 0 -> Eable H/W reboot with P4.3
B4 : 0 -> Enable H/W reboot with P2.6, P2.7
B1 : 0 -> MOVC Inhibited
B0 : 0 -> Data out lock
Default 1 for each bit.
Option Bits
B0: Lock bit
This bit is used to protect the customer's program code in the W79E(L)632. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
Flash EPROM data and Special Setting Registers can not be accessed again.
B1: MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space will
always be able to access the ROM data in both internal and external memory. If this bit is logic 1, there
are no restrictions on the MOVC instruction.
B4: H/W Reboot with P2.6 and P2.7
If this bit is set to logic 0, enable to reboot 4k LDFlash mode while RST =H, P2.6 = L and P2.7 = L state.
CPU will start from LDFlash to update the user’s program.
B5: H/W Reboot with P4.3
If this bit is set to logic 0, enable to reboot 4k LDFlash mode while RST =H and P4.3 = L state. CPU will
start from LDFlash to update the user’s program
B7: Select clock freqency.
If clock freqency is over 24M hz, then set this bit is H. If clock frequency is less than 24M hz, then clear
this bit.
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Publication Release Date: Nov. 11, 2009
Revision A10