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W79E632A Datasheet, PDF (50/79 Pages) Winbond – 8-BIT MICROCONTROLLER
W79E632A/W79L632A
Watchdog Control
WDIF: WDCON.3 - Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the
watchdog timer. If the Watchdog interrupt is enabled (EIE.4), then an interrupt will occur (if the
global interrupt enable is set and other interrupt requirements are met). Software or any reset
can clear this bit.
WTRF: WDCON.2 - Watchdog Timer Reset flag. This bit is set whenever a watchdog reset occurs.
This bit is useful for determined the cause of a reset. Software must read it, and clear it
manually. A Power-fail reset will clear this bit. If EWT = 0, then this bit will not be affected by
the watchdog timer.
EWT: WDCON.1 - Enable Watchdog timer Reset. This bit when set to 1 will enable the Watchdog
timer reset function. Setting this bit to 0 will disable the Watchdog timer reset function, but will
leave the timer running.
RWT:
WDCON.0 - Reset Watchdog Timer. This bit is used to clear the Watchdog timer and to
restart it. This bit is self-clearing, so after the software writes 1 to it the hardware will
automatically clear it. If the Watchdog timer reset is enabled, then the RWT has to be set by
the user within 512 clocks of the time-out. If this is not done then a Watchdog timer reset will
occur.
Clock Control
WD1, WD0: CKCON.7, CKCON.6 - Watchdog Timer Mode select bits. These two bits select the time-
out interval for the watchdog timer. The reset time is 512 clock longer than the interrupt
time-out value.
The default Watchdog time-out is 217 clocks, which is the shortest time-out period. The EWT, WDIF and
RWT bits are protected by the Timed Access procedure. This prevents software from accidentally
enabling or disabling the watchdog timer. More importantly, it makes it highly improbable that errant code
can enable or disable the watchdog timer. Please refer as below demo program.
org 63h
mov TA,#AAH
mov TA,#55H
clr WDIF
jnb execute_reset_flag,bypass_reset
jmp $
bypass_reset:
mov TA,#AAH
mov TA,#55H
setb RWT
reti
; Test if CPU need to reset.
; Wait to reset
org 300h
start:
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