W79E632A Datasheet, PDF (36/79 Pages) Winbond – 8-BIT MICROCONTROLLER

W79E632A/W79L632A
9. INTERRUPTS
The W79E(L)632 has a two priority level interrupt structure with 11 interrupt sources. Each of the
interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the
interrupts can be globally enabled or disabled.
Interrupt Sources
The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, depending on bits
IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to generate the
interrupt. In the edge triggered mode, the INTx inputs are sampled in every machine cycle. If the sample
is high in one cycle and low in the next, then a high to low transition is detected and the interrupts
request flag IEx in TCON is set. The flag bit requests the interrupt. Since the external interrupts are
sampled every machine cycle, they have to be held high or low for at least one complete machine cycle.
The IEx flag is automatically cleared when the service routine is called. If the level triggered mode is
selected, then the requesting source has to hold the pin low till the interrupt is serviced. The IEx flag will
not be cleared by the hardware on entering the service routine. If the interrupt continues to be held low
even after the service routine is completed, then the processor may acknowledge another interrupt
request from the same source.
The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the
overflow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware
when the timer interrupt is serviced. The Timer 2 interrupt is generated by a logical OR of the TF2 and
the EXF2 flags. These flags are set by overflow or capture/reload events in the timer 2 operation. The
hardware does not clear these flags when a timer 2 interrupt is executed. Software has to resolve the
cause of the interrupt between TF2 and EXF2 and clear the appropriate flag.
The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the time-
out count is reached, the Watchdog timer interrupt flag WDIF (WDCON.3) is set. If the interrupt is
enabled by the enable bit EIE.4, then an interrupt will occur.
All the bits that generate interrupts can be set or reset by hardware, and thereby software initiated
interrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or
clearing a bit in the IE SFR. IE also has a global enable/disable bit EA, which can be cleared to disable
all the interrupts.
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