NUC910ABN Datasheet, PDF (63/669 Pages) Nuvoton Technology Corporation – 32-bit ARM926EJ-S Based Microcontroller

NUC910ABN
32-BIT ARM926EJ-S BASED MCU
PLL Control Register 0（PLLCON0）
PLL Control Register 1（PLLCON1）
Register
PLLCON0
PLLCON1
Address
0xB000_020C
0xB000_0210
R/W
R/W
R/W
Description
PLL Control Register 0
PLL Control Register 1
Reset Value
0x0000_2B63
0x0001_4F64
31
23
15
7
FBDV
30
29
22
21
14
13
6
5
OTDV
28
27
RESERVED
20
19
RESERVED
12
11
FBDV
4
3
26
18
10
2
INDV
25
24
17
16
PWDEN
9
8
1
0
Bits
[16]
[15:7]
[6:5]
[4:0]
Descriptions
PWDEN
FBDV
OTDV
INDV
Power Down Mode Enable
0 = PLL is in normal mode
1 = PLL is in power down mode
PLL VCO Output Clock Feedback Divider
Feedback Divider divides the output clock from VCO of PLL.
PLL Output Clock Divider
OTDV
Divided by
0
0
1
0
1
2
1
0
2
1
1
4
PLL Input Clock Divider
Input Divider divides the input reference clock into the PLL.
Publication Release Date: Jun. 18, 2010
63
Revision: A4