NUC910ABN Datasheet, PDF (130/669 Pages) Nuvoton Technology Corporation – 32-bit ARM926EJ-S Based Microcontroller

NUC910ABN
Bits
[16]
[14]
[11]
[10]
[9]
Descriptions
EnTXINTR
EnCFR
EnRxBErr
EnRDU
EnDEN
32-BIT ARM926EJ-S BASED MCU
Enable Transmit Interrupt
The EnTXINTR controls the Tx interrupt generation.
If EnTXINTR is enabled and TXINTR of MISTA register is high, EMC generates
the Tx interrupt to CPU. If EnTXINTR is disabled, no Tx interrupt is generated
to CPU even the status bits 17~24 of MISTA are set and the corresponding
bits of MIEN are enabled. In other words, if S/W wants to receive Tx
interrupt from EMC, this bit must be enabled. And, if S/W doesn’t want to
receive any Tx interrupt from EMC, disables this bit.
1’b0: TXINTR of MISTA register is masked and Tx interrupt generation is
disabled.
1’b1: TXINTR of MISTA register is unmasked and Tx interrupt generation is
enabled.
Enable Control Frame Receive Interrupt
The EnCFR controls the CFR interrupt generation. If CFR of MISTA register is
set, and both EnCFR and EnTXINTR are enabled, the EMC generates the Rx
interrupt to CPU. If EnCFR or EnTXINTR is disabled, no Rx interrupt is
generated to CPU even the CFR of MISTA register is set.
1’b0: CFR of MISTA register is masked from Rx interrupt generation.
1’b1: CFR of MISTA register can participate in Rx interrupt generation.
Enable Receive Bus Error Interrupt
The EnRxBErr controls the RxBerr interrupt generation. If RxBErr of MISTA
register is set, and both EnRxBErr and EnTXINTR are enabled, the EMC
generates the Rx interrupt to CPU. If EnRxBErr or EnTXINTR is disabled, no
Rx interrupt is generated to CPU even the RxBErr of MISTA register is set.
1’b0: RxBErr of MISTA register is masked from Rx interrupt generation.
1’b1: RxBErr of MISTA register can participate in Rx interrupt generation.
Enable Receive Descriptor Unavailable Interrupt
The EnRDU controls the RDU interrupt generation. If RDU of MISTA register
is set, and both EnRDU and EnTXINTR are enabled, the EMC generates the
Rx interrupt to CPU. If EnRDU or EnTXINTR is disabled, no Rx interrupt is
generated to CPU even the RDU of MISTA register is set.
1’b0: RDU of MISTA register is masked from Rx interrupt generation.
1’b1: RDU of MISTA register can participate in Rx interrupt generation.
Enable DMA Early Notification Interrupt
The EnDEN controls the DENI interrupt generation. If DENI of MISTA register
is set, and both EnDEN and EnTXINTR are enabled, the EMC generates the
Rx interrupt to CPU. If EnDEN or EnTXINTR is disabled, no Rx interrupt is
generated to CPU even the DENI of MISTA register is set.
1’b0: DENI of MISTA register is masked from Rx interrupt generation.
1’b1: DENI of MISTA register can participate in Rx interrupt generation.
Publication Release Date: Jun. 18, 2010
130
Revision: A4