NUC910ABN Datasheet, PDF (306/669 Pages) Nuvoton Technology Corporation – 32-bit ARM926EJ-S Based Microcontroller

NUC910ABN
32-BIT ARM926EJ-S BASED MCU
Memory Stick Register Buffer 1 (MSBUF1)
Memory Stick Register Buffer 2 (MSBUF2)
Register
MSBUF1
MSBUF2
Address
0xB000_D06C
0xB000_D070
R/W
R/W
Description
Memory Stick Register Buffer 1
Memory Stick Register Buffer 2
Reset Value
0x0000_0x0000
31
30
29
28
27
26
25
24
DATA[31:24]
23
22
21
20
19
18
17
16
DATA[23:16]
15
14
13
12
11
10
9
8
DATA[15:8]
7
6
5
4
3
2
1
0
DATA[7:0]
Bits
[31:0]
Descriptions
DATA
Data Content of Packet Transfer
This field contains the data of READ/WRITE TPC codes. When software uses
following TPC codes, data will be obtained from (stored in) this field.
READ_REG, GET_INT, WRITE_REG, SET_R/W_REG_ADRS, SET_CMD and
EX_SET_CMD.
This core will always send (store) data from MSB of MSBUF2. For example, if
software wants to WRITE a packet with 1 byte data, you should put the data
at MSBUF2[31:24] and write 0x1 into MSCSR[DCNT] then trigger the core.
The order of transfer will be MSBUF2[31], MSBUF2[30] …, MSBUF2[24]. If
you want to WRITE a packet with 6 bytes data, you should put the data at
MSBUF2[31:0] and MSBUF1[31:16] and write 0x6 into MSCSR[DCNT] then
trigger the core. The order of transfer will be MSBUF2[31:24], …
MSBUF2[7:0], MSBUF1[31:24], MSBUF1[23:16]. The same order will be
applied to READ packet.
MSBUF1
MSBUF2
BYTE 5
BYTE 1
BYTE 6
BYTE 2
BYTE 7
BYTE 3
BYTE 8
BYTE 4
Publication Release Date: Jun. 18, 2010
306
Revision: A4