NUC910ABN Datasheet, PDF (228/669 Pages) Nuvoton Technology Corporation – 32-bit ARM926EJ-S Based Microcontroller

NUC910ABN
32-BIT ARM926EJ-S BASED MCU
Register
Address
USB_FRAME_CNT
0xB000_601C
USB_ADDR
0xB000_6020
CEP_DATA_BUF
0xB000_6028
CEP_CTRL_STAT
0xB000_602C
CEP_IRQ_ENB
0xB000_6030
CEP_IRQ_STAT
0xB000_6034
IN_TRNSFR_CNT
0xB000_6038
OUT_TRNSFR_CNT 0xB000_603C
CEP_CNT
0xB000_6040
SETUP1_0
0xB000_6044
SETUP3_2
0xB000_6048
SETUP5_4
0xB000_604C
SETUP7_6
0xB000_6050
CEP_START_ADDR 0xB000_6054
CEP_END_ADDR
0xB000_6058
DMA_CTRL_STS
0xB000_605C
DMA_CNT
0xB000_6060
EPA_DATA_BUF
0xB000_6064
EPA_IRQ_STAT
0xB000_6068
EPA_IRQ_ENB
0xB000_606C
EPA_DATA_CNT
0xB000_6070
EPA_RSP_SC
0xB000_6074
EPA_MPS
0xB000_6078
EPA_CNT
0xB000_607C
EPA_CFG
0xB000_6080
EPA_START_ADDR 0xB000_6084
EPA_END_ADDR
0xB000_6088
EPB_DATA_BUF
0xB000_608C
EPB_IRQ_STAT
0xB000_6090
EPB_IRQ_ENB
0xB000_6094
R/W Description
Reset Value
R USB frame count register
0x0000_0000
R/W USB address register
0x0000_0000
R/W Control-ep Data Buffer
0x0000_0000
R/W Control-ep Control and Status
0x0000_0000
R/W Control-ep Interrupt Enable
0x0000_0000
R/W Control-ep Interrupt Status
0x0000_1000
R/W In-transfer data count
0x0000_0000
R Out-transfer data count
0x0000_0000
R Control-ep data count
0x0000_0000
R Setupbyte1 & byte0
0x0000_0000
R Setupbyte3 & byte2
0x0000_0000
R Setupbyte5 & byte4
0x0000_0000
R Setupbyte7 & byte6
0x0000_0000
R/W Control EP’s RAM start address
0x0000_0000
R/W Control EP’s RAM end address
0x0000_0000
R/W DMA control and status register
0x0000_0000
R/W DMA count register
0x0000_0000
R/W Endpoint A data register
0x0000_0000
R/W Endpoint A Interrupt status register
0x0000_0002
R/W Endpoint A Interrupt enable register
0x0000_0000
R Data count available in endpoint A buffer 0x0000_0000
R/W Endpoint A response register set/clear
0x0000_0000
R/W Endpoint A maximum packet size register 0x0000_0000
R/W Endpoint A transfer count register
0x0000_0000
R/W Endpoint A configuration register
0x0000_0012
R/W Endpoint A RAM start address
0x0000_0000
R/W Endpoint A RAM end address
0x0000_0000
R/W Endpoint B data register
0x0000_0000
R/W Endpoint B Interrupt status register
0x0000_0002
R/W Endpoint B Interrupt enable register
0x0000_0000
Publication Release Date: Jun. 18, 2010
228
Revision: A4