AT45DQ161 Datasheet, PDF (57/81 Pages) List of Unclassifed Manufacturers – 16-Mbit DataFlash (with Extra 512-Kbits), 2.3V or 2.5V Minimum SPI Serial Flash Memory with Dual-I/O and Quad-I/O Support

21.
Utilizing the RapidS Function
To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full clock cycle must be used
to transmit data back and forth across the serial bus. The DataFlash is designed to always clock its data out on the falling
edge of the SCK signal and clock data in on the rising edge of SCK.
For full clock cycle operation to be achieved, when the DataFlash is clocking data out on the falling edge of SCK, the host
controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller should clock its
data out on the rising edge of SCK in order to give the DataFlash a full clock cycle to latch the incoming data in on the
next rising edge of SCK.
Figure 21-1. RapidS Mode
Slave CS
SCK
1
8
1
8
1
2
3
4
5
6
7
2
3
4
5
6
7
B
A
C
E
D
MOSI
MSB
LSB
BYTE-MOSI
H
G
I
F
MISO
MSB
LSB
BYTE-SO
MOSI = Master Out, Slave In
MISO = Master In, Slave Out
The Master is the host controller and the Slave is the DataFlash.
The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.
The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.
A. Master clocks out first bit of BYTE-MOSI on the rising edge of SCK
B. Slave clocks in first bit of BYTE-MOSI on the next rising edge of SCK
C. Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK
D. Last bit of BYTE-MOSI is clocked out from the Master
E. Last bit of BYTE-MOSI is clocked into the slave
F. Slave clocks out first bit of BYTE-SO
G. Master clocks in first bit of BYTE-SO
H. Slave clocks out second bit of BYTE-SO
I. Master clocks in last bit of BYTE-SO
AT45DQ161 [PRELIMINARY DATASHEET] 57
8790B–DFLASH–10/2013