M0516ZAN Datasheet, PDF (40/71 Pages) List of Unclassifed Manufacturers – ARM Cortex™-M0 32-BIT MICROCONTROLLER

NuMicro^™ M058/M0516 Data Sheet
CCR0.CFL_IE0[2]] (Falling latch Interrupt enable) to decide the condition of interrupt occur.
Capture channel 1 has the same feature by setting CCR0.CRL_IE1[17] and CCR0.CFL_IE1[18].
And capture channel 0 to channel 3 on each group have the same feature by setting the
corresponding control bits in CCR0 and CCR2. For each group, whenever Capture issues
Interrupt 0/1/2/3, the PWM counter 0/1/2/3 will be reload at this moment.
The maximum captured frequency that PWM can capture is confined by the capture interrupt
latency. When capture interrupt occurred, software will do at least three steps, they are: Read
PIIR to get interrupt source and Read CRLRx/CFLRx(x=0 and 3) to get capture value and finally
write 1 to clear PIIR. If interrupt latency will take time T0 to finish, the capture signal mustn’t
transition during this interval (T0). In this case, the maximum capture frequency will be 1/T0. For
example:
HCLK = 50 MHz, PWM_CLK = 25 MHz, Interrupt latency is 900 ns
So the maximum capture frequency will is 1/900ns ≈ 1000 kHz
6.6.2 Features
6.6.2.1 PWM function features:
PWM group has two PWM generators. Each PWM generator supports one 8-bit prescaler, one
clock divider, two PWM-timers (down counter), one dead-zone generator and two PWM outputs.
„ Up to 16 bits resolution
„ PWM Interrupt request synchronized with PWM period
„ One-shot or Auto-reload mode PWM
„ Up to 2 PWM group (PWMA/PWMB) to support 8 PWM channels
6.6.2.2 Capture Function Features:
„ Timing control logic shared with PWM Generators
„ 8 capture input channels shared with 8 PWM output channels
„ Each channel supports one rising latch register (CRLR), one falling latch register (CFLR)
and Capture interrupt flag (CAPIFx)
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Publication Release Date: May 30, 2011
Revision V2.00