M0516ZAN Datasheet, PDF (34/71 Pages) List of Unclassifed Manufacturers – ARM Cortex™-M0 32-BIT MICROCONTROLLER

NuMicro^™ M058/M0516 Data Sheet
6.3.7 Frequency Divider Output
This device is equipped a power-of-2 frequency divider which is composed by16 chained divide-
by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is
reflected to P3.6. Therefore there are 16 options of power-of-2 divided clocks with the frequency
from F_in/2¹ to F_in/2¹⁷ where Fin is input clock frequency to the clock divider.
The output formula is F_out = F_in/2^(N+1), where F_in is the input clock frequency, F_out is the clock
divider output frequency and N is the 4-bit value in FREQDIV.FSEL[3:0].
When write 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When write 0 to
DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low
state and stay in low state.
CLKSEL2.FRQDIV_S[3:2]
22.1184M
11
HCLK
10
Ext. Crystal
00
APBCLK.FRQDIV_EN[6]
FRQDIV_CLK
Figure 6-9 Clock Source of Frequency Divider
FREQDIV.FDIV_EN[4]
0 to 1
Reset Clock
Divider
FRQDIV_CLK
1/2
16 chained
divide-by-2 counter
1/2² 1/2³
…...
1/2¹ 1/2¹
5
6
000
001
:
:
110
111
16 to 1
MUX
P3_DOUT[6]
10 ^P3.6/CLKO
00
FREQDIV.FSEL[3:0]
P3_ALT[6]
P3_MFP[6]
Figure 6-10 Block Diagram of Frequency Divider
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Publication Release Date: May 30, 2011
Revision V2.00