M0516ZAN Datasheet, PDF (39/71 Pages) List of Unclassifed Manufacturers – ARM Cortex™-M0 32-BIT MICROCONTROLLER

NuMicro^™ M058/M0516 Data Sheet
6.6 PWM Generator and Capture Timer
6.6.1 Overview
NuMicro M051^™ series has 2 sets of PWM group supports 4 sets of PWM Generators which can
be configured as 8 independent PWM outputs, PWM0~PWM7, or as 4 complementary PWM
pairs, (PWM0, PWM1), (PWM2, PWM3), (PWM4, PWM5) and (PWM6, PWM7) with 4
programmable dead-zone generators.
Each PWM Generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1,
1/2, 1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM down-
counters for PWM period control, two 16-bit comparators for PWM duty control and one dead-
zone generator. The 4 sets of PWM Generators provide eight independent PWM interrupt flags
which are set by hardware when the corresponding PWM period down counter reaches zero.
Each PWM interrupt source with its corresponding enable bit can cause CPU to request PWM
interrupt. The PWM generators can be configured as one-shot mode to produce only one PWM
cycle signal or auto-reload mode to output PWM waveform continuously.
When PCR.DZEN01 is set, PWM0 and PWM1 perform complementary PWM paired function; the
paired PWM period, duty and dead-time are determined by PWM0 timer and Dead-zone
generator 0. Similarly, the complementary PWM pairs of (PWM2, PWM3), (PWM4, PWM5) and
(PWM6, PWM7) are controlled by PWM2, PWM4 and PWM6 timers and Dead-zone generator 2,
4 and 6, respectively. Refer to figures bellowed for the architecture of PWM Timers.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers the updated value will be load into the 16-bit down counter/
comparator at the time down counter reaching zero. The double buffering feature avoids glitch at
PWM outputs.
When the 16-bit period down counter reaches zero, the interrupt request is generated. If PWM-
timer is set as auto-reload mode, when the down counter reaches zero, it is reloaded with PWM
Counter Register (CNRx) automatically then start decreasing, repeatedly. If the PWM-timer is set
as one-shot mode, the down counter will stop and generate one interrupt request when it reaches
zero.
The value of PWM counter comparator is used for pulse high width modulation. The counter
control logic changes the output to high level when down-counter value matches the value of
compare register.
The alternate feature of the PWM-timer is digital input Capture function. If Capture function is
enabled the PWM output pin is switched as capture input mode. The Capture0 and PWM0 share
one timer which is included in PWM 0; and the Capture1 and PWM1 share PWM1 timer, and etc.
Therefore user must setup the PWM-timer before enable Capture feature. After capture feature is
enabled, the capture always latched PWM-counter to Capture Rising Latch Register (CRLR)
when input channel has a rising transition and latched PWM-counter to Capture Falling Latch
Register (CFLR) when input channel has a falling transition. Capture channel 0 interrupt is
programmable by setting CCR0.CRL_IE0[1] (Rising latch Interrupt enable) and
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Publication Release Date: May 30, 2011
Revision V2.00