KXTIK-1004 Datasheet, PDF (30/54 Pages) List of Unclassifed Manufacturers – 2g/4g/8g Tri-axis Digital Accelerometer Specifications

± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KXTIK-1004
Rev. 2
Dec-2011
OSAA
0
0
0
0
1
1
1
1
OSAB
0
0
1
1
0
0
1
1
OSAC
0
1
0
1
0
1
0
1
Output Data Rate
12.5Hz
25Hz
50Hz
100Hz
200Hz
400Hz
800Hz
Does Not Exist
LPF Roll-Off
6.25Hz
12.5Hz
25Hz
50Hz
100Hz
200Hz
400Hz
Does Not Exist
Table 20. LPF Acceleration Output Data Rate (ODR)
TILT_TIMER
This register is the initial count register for the tilt position state timer (0 to 255 counts). Every count is
calculated as 1/ODR delay period, where the Tilt Position ODR is user-defined per Table 14. A new
state must be valid as many measurement periods before the change is accepted. Note that to properly
change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.
R/W
TSC7
Bit7
R/W
TSC6
Bit6
R/W
TSC5
Bit5
R/W
TSC4
Bit4
R/W
TSC3
Bit3
R/W
R/W
R/W
TSC2
TSC1
TSC0
Bit2
Bit1
Bit0
I²C Address: 0x28h
Reset Value
00000000
WUF_TIMER
This register is the initial count register for the motion detection timer (0 to 255 counts). Every count is
calculated as 1/ODR delay period, where the Motion Wake Up ODR is user-defined per Table 16. A
new state must be valid as many measurement periods before the change is accepted. Note that to
properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.
R/W
WUFC7
Bit7
R/W
WUFC6
Bit6
R/W
WUFC5
Bit5
R/W
WUFC4
Bit4
R/W
WUFC3
Bit3
R/W
R/W
R/W
WUFC2 WUFC1 WUFC0
Bit2
Bit1
Bit0
I²C Address: 0x29h
Reset Value
00000000
TDT_TIMER
This register contains counter information for the detection of a double tap event. When the Directional
Tap^TM ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the Directional
Tap^TM ODR is 800Hz, every count is calculated as 2/ODR delay period. When the Directional Tap^TM
ODR is 1600Hz, every count is calculated as 4/ODR delay period. The Directional Tap^TM ODR is user-
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