KXTIK-1004 Datasheet, PDF (25/54 Pages) List of Unclassifed Manufacturers – 2g/4g/8g Tri-axis Digital Accelerometer Specifications

± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KXTIK-1004
Rev. 2
Dec-2011
OTDTH determines the range of the Directional Tap^TM Output Data Rate (ODR). See Table
15 for additional clarification.
OTDTH = 0 – slower range of Directional Tap^TM ODR’s are available.
OTDTH = 1 – faster range of Directional Tap^TM ODR’s are available.
Bit
LEM
RIM
DOM
UPM
FDM
FUM
Description
Left State
Right State
Down State
Up State
Face-Down State
Face-Up State
Table 13. Tilt Position State Enabling
CTRL_REG3
Read/write control register that provides more feature set control. Note that to properly change the
value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.
R/W
SRST
Bit7
R/W
OTPA
Bit6
R/W
OTPB
Bit5
R/W
DCST
Bit4
R/W
OTDTA
Bit3
R/W
R/W
R/W
OTDTB OWUFA OWUFB
Bit2
Bit1
Bit0
I²C Address: 0x1Dh
Reset Value
01001101
SRST initiates software reset, which performs the RAM reboot routine. This bit will remain 1
until the RAM reboot routine is finished.
SRST = 0 – no action
SRST = 1 – start RAM reboot routine
Note for I2C Communication: Setting SRST = 1 will NOT result in an ACK, since the part
immediately enters the RAM reboot routine. NACK may be used to confirm this
command.
OTPA, OTPB sets the output data rate for the Tilt Position function per Table 14. The default
Tilt Position ODR is 12.5Hz.
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