KXTIK-1004 Datasheet, PDF (29/54 Pages) List of Unclassifed Manufacturers – 2g/4g/8g Tri-axis Digital Accelerometer Specifications

± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KXTIK-1004
Rev. 2
Dec-2011
TMEN = 0 – alternate tap masking scheme disabled
TMEN = 1 – alternate tap masking scheme enabled
DATA_CTRL_REG
Read/write control register that configures the acceleration outputs. Note that to properly change the
value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
HPFROA HPROB
0
OSAA OSAB OSAC
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
I²C Address: 0x21h
00000010
HPFROA, HPFROB sets the roll-off frequency for the first-order high-pass filter in conjunction
with the output data rate (OWUFA, OWUFB) that is chosen for the HPF acceleration outputs
that are used in the Motion Wake Up (WUF) application per Table 19. Note that this roll-off
frequency is also applied to the X, Y and Z high-pass filtered outputs.
High-Pass Filter Configuration
HPFROA HPFROB Beta HPF Roll-Off (Hz)
0
0
7/8
ODR / 50
0
1
15/16
ODR / 100
1
0
31/32
ODR / 200
1
1
63/64
ODR / 400
Table 19. High-Pass Filter Roll-Off Frequency
OSAA, OSAB, OSAC sets the output data rate (ODR) for the low-pass filtered acceleration
outputs per Table 20.
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