KXTIK-1004 Datasheet, PDF (12/54 Pages) List of Unclassifed Manufacturers – 2g/4g/8g Tri-axis Digital Accelerometer Specifications

± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KXTIK-1004
Rev. 2
Dec-2011
It is mandatory that receiving devices acknowledge (ACK) each transaction. Therefore, the transmitter must
release the SDA line during this ACK pulse. The receiver then pulls the data line low so that it remains stable
low during the high period of the ACK clock pulse. A receiver that has been addressed, whether it is Master or
Slave, is obliged to generate an ACK after each byte of data has been received. To conclude a transaction,
the Master must transmit a stop condition (P) by transitioning the SDA line from low to high while SCL is high.
The I²C bus is now free.
Writing to a KXTIK 8-bit Register
Upon power up, the Master must write to the KXTIK’s control registers to set its operational mode. Therefore,
when writing to a control register on the I²C bus, as shown Sequence 1 on the following page, the following
protocol must be observed: After a start condition, SAD+W transmission, and the KXTIK ACK has been
returned, an 8-bit Register Address (RA) command is transmitted by the Master. This command is telling the
KXTIK to which 8-bit register the Master will be writing the data. Since this is I²C mode, the MSB of the RA
command should always be zero (0). The KXTIK acknowledges the RA and the Master transmits the data to
be stored in the 8-bit register. The KXTIK acknowledges that it has received the data and the Master transmits
a stop condition (P) to end the data transfer. The data sent to the KXTIK is now stored in the appropriate
register. The KXTIK automatically increments the received RA commands and, therefore, multiple bytes of
data can be written to sequential registers after each Slave ACK as shown in Sequence 2 on the following
page.
Reading from a KXTIK 8-bit Register
When reading data from a KXTIK 8-bit register on the I²C bus, as shown in Sequence 3 on the next page, the
following protocol must be observed: The Master first transmits a start condition (S) and the appropriate Slave
Address (SAD) with the LSB set at ‘0’ to write. The KXTIK acknowledges and the Master transmits the 8-bit
RA of the register it wants to read. The KXTIK again acknowledges, and the Master transmits a repeated start
condition (Sr). After the repeated start condition, the Master addresses the KXTIK with a ‘1’ in the LSB
(SAD+R) to read from the previously selected register. The Slave then acknowledges and transmits the data
from the requested register. The Master does not acknowledge (NACK) it received the transmitted data, but
transmits a stop condition to end the data transfer. Note that the KXTIK automatically increments through its
sequential registers, allowing data to be read from multiple registers following a single SAD+R command as
shown below in Sequence 4 on the following page.
If a receiver cannot transmit or receive another complete byte of data until it has performed some other
function, it can hold SCL low to force the transmitter into a wait state. Data transfer only continues when the
receiver is ready for another byte and releases SCL.
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