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SI5022 Datasheet, PDF (9/22 Pages) List of Unclassifed Manufacturers – MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMP
Si5022/Si5023
Table 4. AC Characteristics (PLL Characteristics)
(VDD=2.5 V ± 5% for Si5022 or 3.3 V ± 5% for Si5023, TA = –40°C to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Jitter Tolerance
(OC-48)*
JTOL(PP)
f = 600 Hz
40
f = 6000 Hz
4
f = 100 kHz
4
f = 1 MHz
0.4
Jitter Tolerance
(OC-12 Mode)*
JTOL(PP)
f = 30 Hz
40
f = 300 Hz
4
f = 25 kHz
4
f = 250 kHz
0.4
Jitter Tolerance
(OC-3 Mode)*
JTOL(PP)
f = 30 Hz
60
f = 300 Hz
6
f = 6.5 kHz
6
f = 65 kHz
0.6
Jitter Tolerance (Gigabit Ethernet) TJT(PP) IEEE 802.3z Clause 38.68 600
Receive Data Total Jitter
Tolerance
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
UIPP
—
UIPP
—
UIPP
—
UIPP
—
UIPP
—
UIPP
—
UIPP
—
UIPP
—
UIPP
—
UIPP
—
UIPP
—
UIPP
—
ps
Jitter Tolerance (Gigabit Ethernet) DJT(PP) IEEE 802.3z Clause 38.69 370
Receive Data Deterministic Jitter
Tolerance
RMS Jitter Generation*
JGEN(RMS) with no jitter on serial data —
Peak-to-Peak Jitter Generation*
JGEN(PP) with no jitter on serial data
—
Jitter Transfer Bandwidth*
JBW
OC-48 Mode
—
OC-12 Mode
—
TBD
3.0
25
—
—
—
ps
5.0 mUI
55
mUI
2.0 MHz
500 kHz
Jitter Transfer Peaking*
Acquisition Time
(Reference clock applied)
OC-3 Mode
—
—
130 kHz
JP
—
0.03
0.1
dB
TAQ
After falling edge of
1.45
1.5
1.7
ms
PWRDN/CAL
From the return of valid
40
data
60
150
µs
Acquisition Time
(Reference-less operation)
TAQ
After falling edge of
TBD TBD TBD ms
PWRDN/CAL
From the return of valid TBD TBD TBD ms
data
Reference Clock Range
19.44 — 168.75 MHz
Input Reference Clock Frequency
Tolerance
CTOL
–100
—
100 ppm
Frequency Difference at which
Receive PLL goes out of Lock
(REFCLK compared to the divided
down VCO clock)
TBD 600 TBD ppm
Frequency Difference at which
Receive PLL goes into Lock (REF-
CLK compared to the divided
down VCO clock)
TBD 300 TBD ppm
*Note: As defined in Bellcore specifications: GR-253-CORE, Issue 2, December 1995. Using PRBS 223 – 1 data pattern.
Preliminary Rev. 0.46
9