SI5022 Datasheet, PDF (1/22 Pages) List of Unclassifed Manufacturers – MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMP

Si5022/Si5023
PRELIMINARY DATA SHEET
MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMP
Features
High Speed Clock and Data Recovery device with Integrated Limiting Amp:
! Supports OC-48/12/3, STM-16/4/1, ! External Reference Not Required
Gigabit Ethernet, and 2.7 Gbps FEC ! Jitter Generation 3.0 mUI_RMS(TYP)
! DSPLL™ Technology
! Loss-of-signal Level Alarm
! Low Power—370 mW (TYP)
! Data Slicing Level Control
! Small Footprint: 5 mm x 5 mm
! Bit-Error-Rate Alarm
! 10 mV_PP Differential Sensitivity
! 2.5 V (Si5022) or 3.3 V (Si5023) Supply
Applications
! SONET/SDH/ATM Routers
! Add/Drop Multiplexers
! Digital Cross Connects
! Gigabit Ethernet Interfaces
! SONET/SDH Test Equipment
! Optical Transceiver Modules
! SONET/SDH Regenerators
! Board Level Serial Links
Ordering Information:
See page 14.
Pin Assignments
Si5022/23
Description
The Si5022/23 is a fully integrated, high performance limiting amp and clock and
data recovery (CDR) IC for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-48/12/3, STM-16/4/1, or
Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also provided
for OC-48/STM-16 applications that employ forward error correction (FEC). An
external reference clock is not required; applications with or without an external
reference clock are supported. Silicon Laboratories’ DSPLL^™ technology
eliminates sensitive noise entry points thus making the PLL less susceptible to
board-level interaction and helping to ensure optimal jitter performance.
The Si5022/23 represents a new standard in low jitter, low power, small size, and
integration for high speed LA/CDRs. It operates from either a 3.3 V (Si5023) or
2.5 V (Si5022) supply over the industrial temperature range (–40°C to 85°C).
Functional Block Diagram
RATESEL0
RATESEL1
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
LOL
28 27 26 25 24 23 22
1
21 VDD
2
20 REXT
3
19 RESET/CAL
4
GND
Pad
18 VDD
5
17 DOUT+
6
16 DOUT–
7
15 TDI
8 9 10 11 12 13 14
Top View
DSQLCH
D IN +
D IN –
2 _{Lim iting}
AMP
LOS_LVL
Squelch
Control
R etim er
2
BUF
DSPLL^TM
Phase-Locked
Loop
2
2
BUF
Control
Bias Gen
DOUT+
DOUT–
CLKDSBL
CLKOUT+
CLKOUT–
LOL
R E S E T /C AL
SLICE_LVL
LTR
R ATS E L [1:0]
LOS
BER_LVL
REFCLK+
REFCLK–
B ER_ALM _(Optional)
REXT
Preliminary Rev. 0.46 5/01
Copyright © 2001 by Silicon Laboratories
Si5022/23-DS046
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).