SI5022 Datasheet, PDF (19/22 Pages) List of Unclassifed Manufacturers – MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMP

Si5022/Si5023
Pin #
19
20
22,23
24
26
27
28
GND Pad
Table 9. Si5022/23 Pin Descriptions (Continued)
Pin Name
RESET/CAL
REXT
CLKOUT–,
CLKOUT+
CLKDSBL
BER_LVL
BER_ALM
NC
GND
I/O Signal Level
Description
I
LVTTL Reset/Calibrate.
Driving this input high for at least 1 µS will reset
internal device circuitry. A high to low transition on
this pin will force a DSPLL calibration. For normal
operation, drive this pin low. This pin should be
used to force a DSPLL calibration on power-up to
ensure optimal jitter performance.
Note: This input has a weak internal pull-down.
External Bias Resistor.
This resistor is used to establish internal bias cur-
rents within the device. This pin must be connected
to GND through a 10 kΩ (1%) resistor.
O
CML
Differential Clock Output.
The output clock is recovered from the data signal
present on DIN except when LTR is asserted or the
LOL state has been entered.
I
LVTTL Clock Disable.
When this input is high, the CLKOUT output drivers
are disabled. For normal operation, this pin should
be low.
Note: This input has a weak internal pull-down.
I
Bit Error Rate Level Control.
The BER threshold level is set by applying a volt-
age to this pin. The applied voltage is mapped to
one of 64 BER threshold levels. When the BER
exceeds the programmed threshold, BER_ALM is
driven low. If this pin is tied to GND, BER_ALM is
disabled. If it is tied to V_DD, BER_LVL defaults to
10^–3 BER
O
LVTTL Bit Error Rate Alarm.
This pin will be driven low to indicate that the BER
threshold set by BER_LVL has been exceeded. The
alarm will clear after the BER rate has improved by
approximately a factor of 2.
No Connect.
Leave this pin unconnected.
GND
Supply Ground.
Nominally 0.0 V. The GND pad found on the bottom
of the 28-lead micro leaded package (see
Figure 14) must be connected directly to supply
ground. Minimize the ground path inductance for
optimal performance.
Preliminary Rev. 0.46
19