SLGSSTVF16859 Datasheet, PDF (8/11 Pages) List of Unclassifed Manufacturers – DDR 13 to 26 Bit Registered Buffer

From output
under test
SLGSSTVF16859H/V
.^{Test Point}
C_L = 30pF⁽¹⁾
.
R_L = 500Ω
Load Circuit
RESET
LVCMOS
input
VDD/2
VDD/2
VDD
0V
t_INACT
t_ACT
I_DD(2)
90%
10%
Voltage and Current Waveforms
Inputs Active and Inactive Times
I_DDH
I_DDL
t_w
Input
V_REF
V_IH
V_REF
V_IL
Voltage Waveforms - Pulse Duration
Timing
Input
V_ICR
V_I(PP)
t_S
t_H
Input
V_REF
V_IH
V_REF
V_IL
Voltage Waveforms - Setup and Hold Times
Timing
Input
V_ICR
V_ICR
V_I(PP)
t_PLH
t_PHL
Output
VDDQ/2
V_OH
VDDQ/2
V_OL
Voltage Waveforms - Propagation Delay Times
RESET
V_IH
LVCMOS
VDD/2
input
V_IL
t_PHL
Output
VDDQ/2
V_OH
V_OL
Voltage Waveforms - Propagation Delay Times
Notes:
1. C_L includes measurement probe and jig capacitance.
2. Conditions for I_DD testing are with clock and data inputs at V_DD or GND, and I_O = 0mA
3. All input pulses are supplied by generators having: Zo=50Ω,
input slew rate = 1 V/ns + 20% ( unless otherwise specified).
4. The outputs are measured individually with one transition per measurement.
5. V_IH = V_REF + 310mV (AC levels) for differential inputs. V_IH = V_DDQ for LVCMOS input.
6. V_IL = V_REF - 310mV (AC levels) for differential inputs. V_IL = GND for LVCMOS input.
7. t_PLH = t_PHL = t_PD
Silego Technology Inc.
[phone]
PRELIMINARY
8
Data is subject to change.
May 28, 2003