SLGSSTVF16859 Datasheet, PDF (7/11 Pages) List of Unclassifed Manufacturers – DDR 13 to 26 Bit Registered Buffer

SLGSSTVF16859H/V
Timing Requirements¹:
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
V_DD = 2.5V + 0.2V
MIN MAX
f_clock Clock frequency
210
t_W
Pulse duration
CLK,CLK high or low
2.5
t_{ACT Differential active time}⁵
22
t_{INACT Differential inactive time}⁶
22
t_S
Setup time, fast slew rate^{2 & 4} _{Data before CLK , CLK}
Setup time, slow slew rate^{3 & 4}
0.65
0.75
t_H
Hold time, fast slew rate^{2 & 4}
Hold time, slow slew rate^{3 & 4 Data after CLK}
, CLK
0.65
0.8
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of > 1V/ns.
3 - For data signal input slew rate of > 0.5V/ns and < 1V/ns.
4 - CLK, CLK signals input slew rate of > 1V/ns.
5 - Data input must be held low for a minimum time (t_ACT max) after RESET driven high
6 - Data and CLK,CLK inputs must be held at valid logic (high or low) levels for a minimum time
(t_INACT max) after RESET driven low
Switching Characteristics:( For PC1600/2100/2700)
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
From
(Input)
To
(Output)
V_DD = 2.5V + 0.2V
MIN TYP MAX
f_max
210
t_PD CLK, CLK
Q
1.1
2.6
t_PDSS1 CLK, CLK
Q
1.1
2.9
t_PHL RESET
Q
5
UNITS
MHz
ns
ns
ns
Switching Characteristics:( For PC3200)
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
From
(Input)
To
(Output)
V_DD = 2.6V + 0.1V
MIN TYP MAX
f_max
210
t_PD CLK, CLK
Q
1.1
2.2
t_PDSS1 CLK, CLK
Q
1.1
2.48
t_PHL RESET
Q
5
UNITS
MHz
ns
ns
ns
Silego Technology Inc.
[phone]
PRELIMINARY
7
Data is subject to change.
May 28, 2003