SLGSSTVF16859 Datasheet, PDF (6/11 Pages) List of Unclassifed Manufacturers – DDR 13 to 26 Bit Registered Buffer

SLGSSTVF16859H/V
SLGSSTVF16859V DC Electrical Characteristics - ( For PC3200)
T_A = 0 - 70^oC; V_DD = 2.6 +/-0.1V, V_DDQ = 2.6 +/-0.1V; (unless otherwise stated)
SMBL PARAMETERS
CONDITIONS
V_DDQ
MIN
V_IK
V_OH
I_I = -18mA
I_OH = -100µA
2.5V
2.5V -2.7V V_DDQ -
0.2
I_OH = -8mA
2.5V 1.95
V_OL
I_OL = 100µA
2.5V -2.7V
I_OL = 8mA
2.5V
I_I
All Inputs
V_I = V_DD or GND
2.7V
Standby (Static) RESET = GND
I_{DD Operating (Static) VI = VIH(AC) or VIL(AC),}
RESET = V_DD
2.7V
I_DDD
Dynamic
operating
(clock only)
Dynamic
Operating
(per each data
input)
RESET = V_DD,
V_I = V_IH(AC) or V_IL(AC),
CLK & CLK switching
50% duty cycle
RESET = V_DD,
V_I = V_IH(AC) or V_IL(AC),
CLK & CLK switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
I_O = 0
2.6V
r_OH Output High
I_OH = -20mA
2.5V-2.7V 7
r_OL Output Low
I_OL = 20mA
2.5V-2.7V 7
r_O(D) [r_OH - r_OL] each _{IO = 20mA, TA = 25}^o_C
separate bit
2.6V
Data Inputs
V_I = V_REF + 310 mV
C_i
CLK and CLK V_ICR=1.25V, V_I(PP) = 360mV
2.5
2.5V
2.5
RESET
V_I = V_DD or GND
2.5
TYP
52
75
15
13.5
13
MAX UNITS
-1.2
V
0.2
0.35
+5
µA
10
µA
mA
µΑ/
ΜΗz
µΑ/
clock
MHZ/
data
20
Ω
20
Ω
4
Ω
3.5
3.5
pF
3.5
Silego Technology Inc.
[phone]
PRELIMINARY
6
Data is subject to change.
May 28, 2003