SLGSSTVF16859 Datasheet, PDF (1/11 Pages) List of Unclassifed Manufacturers – DDR 13 to 26 Bit Registered Buffer

DDR 13 to 26 Bit Registered Buffer
Applications:
• PC1600/2100/2700/3200 DDR memory modules
• 1:2 Outputs for stacked DDR DIMMS
• SSTL_2 compatible data registers
SLGSSTVF16859H/V
Features:
• Compatible with JEDEC standard SSTV16859
• Differential Clock inputs
• SSTL_2 data input signaling
• Supports SSTL_2 class I output specifications
• Output circuitry minimizes effects of SSO
and unterminated lines
• LVCMOS input levels on RESET pin
• 2.3V-2.7V Operation for PC1600/2100/2700
• 2.5V-2.7V Operation for PC3200
• Max Clock frequency > 210MHz
Block Diagram
CLK ⁴⁸
CLK ⁴⁹
RESET ⁵¹
D1 ³⁵
. VREF ⁴⁵
._R
. ^{. . CLK}
D1
16 _Q1A
32 _Q1B
To 12 other channels
Pin Configuration
Q13A 1
Q12A 2
Q11A 3
Q10A 4
Q9A 5
VDDQ 6
GND 7
Q8A 8
Q7A 9
Q6A 10
Q5A 11
Q4A ₁₂
Q3A ₁₃
Q2A ₁₄
GND ₁₅
Q1A ₁₆
Q13B ₁₇
VDDQ ₁₈
Q12B ₁₉
Q11B ₂₀
Q10B ₂₁
Q9B ₂₂
Q8B ₂₃
Q7B ₂₄
Q6B 25
GND 26
VDDQ 27
Q5B 28
Q4B 29
Q3B 30
Q2B 31
Q1B 32
64 VDDQ
63 GND
62 D13
61 D12
60 VDD
59 VDDQ
58 GND
57 D11
56 D10
55 ^D9
54 ^GND
53 ^D8
52 ^D7
51 ^RESET
50 ^GND
49 ^CLK
48 ^CLK
47 ^VDDQ
46 ^VDD
45 ^VREF
44 ^D6
43 ^GND
42 ^D5
41 ^D4
40 D3
39 GND
38 VDDQ
37 VDD
36 D2
35 D1
34 GND
33 VDDQ
64-Pin TSSOP
6.1mm body, 0.50mm pitch
Truth Table
Inputs
RESET CLK CLK D
L X, or X, or X, or
Floating Floating Floating
H
H
H
L
H L or H L or H X
Q Outputs
Q
L
H
L
Q₀₍₂₎
Notes:
1. H = High Signal Level
L = Low Signal Level
= Transition LOW-to-HIGH
= Transition HIGH-to-LOW
X = Don’t care
2. Output level prior to indicated steady state
input conditions established.
Silego Technology Inc.
[phone]
PRELIMINARY
1
Data is subject to change.
May 28, 2003