HMS87C5216 Datasheet, PDF (71/76 Pages) List of Unclassifed Manufacturers – CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR UR(Universal Remocon) & WIRELESS KEYBOARD

HMS87C5216
fex (MHz)
ps 0
ps 1
ps 2
ps 3
ps 4
ps 5
ps 6
ps 7
ps 8
ps 9
ps 10
ps 11
ps 12
4 MHz
frequency
period
4 MHz
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
62.5 KHz
31.25 KHz
15.63 KHz
7.183 KHz
3.906 KHz
1.953 KHz
0.976 KHz
250 ns
500 ns
1 us
2 us
4 us
8 us
16 us
32 us
64 us
128 us
256 us
512 us
1024 us
2 MHz
frequency
period
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
62.5 KHz
31.25 KHz
15.63 KHz
7.183 KHz
3.906 KHz
1.953 KHz
0.976 KHz
0.488 KHz
500 ns
1 us
2 us
4 us
8 us
16 us
32 us
64 us
128 us
256 us
512 us
1024 us
2048 us
Table 18-1 ps output perio Basic Interval Timer
The HMS87C5216 and GMS81C1408 has one 8-bit Basic Inter-
(only fxin÷2048) and Timer0.
val Timer that is free-run, can not stop. Block diagram is shown
in Figure 18-3.The 8-bit Basic interval timer register (BITR) is
increased every internal count pulse which is divided by prescal-
er. Since prescaler has divided ratio by 8 to 1024, the count rate
is 1/8 to 1/1024 of the oscillator frequency. As the count over-
flows from FF_H to 00_H, this overflow causes to generate the Basic
interval timer interrupt. The BITF is interrupt request flag of Ba-
If the STOP instruction executed after writing “1” to bit RCWDT
of CKCTLR, it goes into the internal RC oscillated watchdog tim-
er mode. In this mode, all of the block is halted except the internal
RC oscillator, Basic Interval Timer and Watchdog Timer. More
detail informations are explained in Power Saving Function. The
bit WDTON decides Watchdog Timer or the normal 7-bit timer
sic interval timer.
When write “1” to bit BTCL of CKCTLR, BITR register is
cleared to “0” and restart to count-up. The bit BTCL becomes “0”
after one machine cycle by hardware.
Note: All control bits of Basic interval timer are in CKCTLR
register which is located at same address of BITR (address
EC_H). Address EC_H is read as BITR, written to CKCTLR.
Therefore, the CKCTLR can not be accessed by bit manip-
If the STOP instruction executed after writing “1” to bit WAKE-
ulation instruction.
UP of CKCTLR, it goes into the wake-up timer mode. In this
mode, all of the block is halted except the oscillator, prescaler
.
RCWDT
BTS[2:0]
÷8
÷ 16
3
÷ 32
fxin
÷ 64
÷ 128
8
MUX
0
÷ 256
÷ 512
1
÷ 1024
Internal RC OSC
BTCL
Clear
BITR (8BIT)
BITIF
To Watchdog Timer
Basic Interval Timer
Interrupt
Figure 18-3 Block Diagram of Basic Interval Timer
SEP. 2004 Ver 1.01