88E1111 Datasheet, PDF (54/252 Pages) List of Unclassifed Manufacturers – Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

88E1111
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
2.2.4 Reduced Pin Count TBI (RTBI)
The 88E1111 device supports RTBI. The RTBI interface pin mapping is shown below. This interface supports 1000
Mbps mode of operation. The RTBI to copper interface is selected by setting HWCFG_MODE[3:0] bits to ‘1001’.
Table 21: RTBI Signal Mapping
88E1111 Device Pin Name
GTX_CLK
TX_EN
RTBI Spec
Pin Name
TXC
TD4_TD9
TXD[3:0]
TD[3:0]
RX_CLK
RX_DV
RXC
RD4_RD9
RXD[3:0]
RD[3:0]
Description
125 MHz transmit clock ± 50 ppm tolerance.
Transmit - Code Group bits 4 and 9. TX_EN presents
bit 4 on the rising edge of GTX_CLK and bit 9 on the
falling edge of GTX_CLK.
Transmit - Code Group bits 0 to 3 and 5 to 8.
TXD[3:0] runs at a double data rate with bits [3:0] pre-
sented on the rising edge of GTX_CLK and bits [8:5]
on the falling edge of GTX_CLK.
125 MHz receive clock ±50 ppm tolerance.
Receive Data - Code Group bits 4 and 9. RX_DV pre-
sents bit 4 of the 10-bit Code Group on the rising
edge of RX_CLK, and bit 9 on the falling edge of
RX_CLK.
Receive Data. RD[3:0] run at a double data rate with
bits [3:0] presented on the rising edge of RX_CLK,
and bits [8:5] on the falling edge of RX_CLK.
Figure 11: RTBI Signal Diagram
MAC
TXC
TD4_TD9
TD[3:0]
RXC
RD4_RD9
RD[3:0]
GTX_CLK
TX_EN
TXD[3:0]
PHY
RX_CLK
RX_DV
RXD[3:0]
Doc. No. MV-S100649-00, Rev. E
Page 54
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2004 Marvell
November 19, 2004, Advance