88E1111 Datasheet, PDF (34/252 Pages) List of Unclassifed Manufacturers – Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

88E1111
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Table 12: Clock/Configuration/Reset/I/O (Continued)
117-TFBGA
Pin #
J9
96-BCC
Pin #
54
128-PQFP
Pin #
75
Pin Name
XTAL2
Pin
Ty p e
0
K3
28
36
RESETn
I
L4
27
37
COMA
I
Description
Reference Clock. 25 MHz ± 50 ppm toler-
ance crystal reference. When the XTAL2
pin is not connected, it should be left float-
ing. There is no option for a 125 MHz crys-
tal. See "Crystal Oscillator" Application
Note for details.
Hardware reset. Active low. XTAL1 must be
active for a minimum of 10 clock cycles
before the rising edge of RESETn.
RESETn must be pulled high for normal
operation.
COMA disables all active circuitry to draw
absolute minimum power. The COMA
power mode can be activated by asserting
high on the COMA pin. To deactivate the
COMA power mode, tie the COMA pin low.
Upon deactivating COMA mode, the
88E1111 device will continue normal opera-
tion.
The COMA power mode cannot be
enabled as long as hardware reset is
enabled.
In COMA mode, the PHY cannot wake up
on its own by detecting activity on the CAT
5 cable.
Table 13: Test
117-TFBGA
Pin #
M5
M6
96-BCC
Pin #
37
38
128-PQFP
Pin #
53
54
Pin Name
HSDAC+
HSDAC-
Pin
Ty p e
Analog
PD
Description
Test pins. These pins should be left floating
but brought out for probing.
Table 14: Control and Reference
117-TFBGA
Pin #
M2
96-BCC
Pin #
30
128-PQFP
Pin #
39
Pin Name
RSET
Pin
Ty p e
Analog
I
Description
Constant voltage reference. External 5.0
kohm 1% resistor connection to VSS
required for each pin.
Doc. No. MV-S100649-00, Rev. E
Page 34
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2004 Marvell
November 19, 2004, Advance