88E1111 Datasheet, PDF (169/252 Pages) List of Unclassifed Manufacturers – Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Register Description
Table 90: Interrupt Status Register
Page 1, Register 19
Bits Field
Mode HW
SW
Description
Rst
Rst
6:5
Reserved
These bits must be read and left unchanged when per-
forming a write.
4
Fiber Energy
RO
0x0
0x0
Fiber Energy Detect changed has effect only when
Detect
mode is 0000, 0110 or 1110.
Changed
1 = Fiber Energy Detect state changed
0 = No Fiber Energy Detect state change detected
3:0
Reserved
These bits must be read and left unchanged when per-
forming a write.
Table 91: Extended PHY Specific Control Register
Page Any, Register 20
Bits Field
15
Block Carrier
Extension Bit
Mode HW
Rst
R/W
0x0
14
Line Loopback R/W
0x0
13
Reserved
12
Disable Link
R/W
0x0
Pulses
11:9 Downshift
counter
R/W
0x6
SW
Rst
0x0
0x0
0x0
Update
Description
1 = Enable Block Carrier Extension
0 = Disable Block Carrier Extension
Refer to the White Paper "TRR Byte Stuffing and MACs"
for details.
In GMII mode, Register 20.15 is the register bit used to
block carrier extension.
1 = Enable Line Loopback
0 = Normal Operation
This bit must be read and left unchanged when perform-
ing a write.
1 = Disable Link Pulse
0 = Enable Link Pulse
Changes to these bits are disruptive to the normal oper-
ation; therefore, any changes to these registers must be
followed by software reset to take effect.
1x, 2x, ...8x is the number of times the PHY attempts to
establish Gigabit link before the PHY downshifts to the
next highest speed.
000 = 1x 100 = 5x
001 = 2x 101 = 6x
010 = 3x 110 = 7x
011 = 4x 111 = 8x
Note: Bit 9 is set to 0 when mode is one of these:
0010, 0011, 0111, 1000, 1001, 1100 or 1101.
Copyright © 2004 Marvell
November 19, 2004, Advance
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S100649-00, Rev. E
Page 169