82C881 Datasheet, PDF (30/46 Pages) List of Unclassifed Manufacturers – FireLink 1394 OHCI Link Controller

FireLink 1394 OHCI
82C881
7
6
5
4
3
2
1
0
PCICFG 47h
PMC Register (RO) - Byte 1
PME Support:
01000 = The Link controller supports PME# generation from D3hot.
Default = 40h
D2 device state D1 device state
support:
support:
Reserved
0 = No
0 = No
PCICFG 48h
PCICFG 49h
PCICFG 4Ah
PMCSR_BSE (RO)
Data Register (RO)
PMCSR Register - Byte 0
Reserved
Default = 00h
Default = 00h
Default = 00h
PowerState (R/W):
00 = D0
01 = D1 (Not Supported)
10 = D2 (Not Supported)
11 = D3hot
This field is used both to
determine the current power state
and to set a new power state.
Unsupported states will be
ignored when written to.
PCICFG 4Bh
PME Status
(R/W):
This bit is set
when a PME
event is
generated.
Data_Scale (RO):
00 = Data register is not
supported
Write 1 to clear.
PMCSR Register - Byte 1
Data_Select (RO):
0000 = Data register is not supported
Default = 00h
PME_En (R/W):
0 = PME#
assertion is
disabled
1 = PME# is
asserted
when PME_
Status = 1
PCICFG 4Ch
Reserved
Reserved
PCICFG 4Dh - 4Fh
GPIO3 Data
Read:
Input Mode –
Returns value
on GPIO3 pin
Output Mode –
Returns last
value written
Write:
Input Mode –
No function
Output Mode –
Sets value on
GPIO3 pin
Miscellaneous Control Register
GPIO3 Mode GPIO2 Data GPIO2 Mode
0 = Output
1 = Input
Read:
Input Mode –
Returns value
on GPIO2 pin
Output Mode –
Returns last
value written
0 = Output
1 = Input
Write:
Input Mode –
No function
Output Mode –
Sets value on
GPIO2 pin
Reserved
Default = 00h
CLKRUN
Support
Reserved
“Enable”
indicates that
the chip will
allow PCICLK
to stop per the
CLKRUN#
protocol
0 = Disable
1 = Enable
Default = 00h
®
Page 26
912-2000-031
Revision: 1.0