82C881 Datasheet, PDF (11/46 Pages) List of Unclassifed Manufacturers – FireLink 1394 OHCI Link Controller

FireLink 1394 OHCI
82C881
3.4 Signal Descriptions
3.4.1 PCI Bus Interface Signals
Signal Name
Pin
No.
Pin
Type
AD[31:0]
Refer to
I/O
Pin
Diagram
C/BE[3:0]#
28, 41,
I/O
53, 65
PAR
52
O
FRAME#
43
I/O
(s/t/s)
Signal Description
Address and Data Lines 31 through 0: This bus carries the address and/or
data during a PCI bus cycle. A PCI bus cycle has two phases - an address phase
which is followed by one or more data phases. During the initial clock of the bus
cycle, the AD bus contains a 32-bit physical byte address. AD[7:0] is the least
significant byte (LSB) and AD[31:24] is the most significant byte (MSB). After the
first clock of the cycle, the AD bus contains data.
When the 82C881 is the target, AD[31:0] are inputs during the address phase.
For the data phase(s) that follow, the 82C881 may supply data on AD[31:0] in the
case of a read or accept data in the case of a write.
When the 82C881 is the master, it drives a valid address on AD[31:2] during the
address phase, and drives write or accepts read data on AD[31:0] during the data
phase. As a master, the 82C881 always drives AD[1:0] low.
Bus Command and Byte Enables 3 through 0: These signals provide the
command type information during the address phase and carry the byte enable
information during the data phase. C/BE0# corresponds to byte 0, C/BE1# to byte
1, C/BE2# to byte 2, and C/BE3# to byte 3.
If the 82C881 is the initiator of a PCI bus cycle, it drives C/BE[3:0]#. When it is
the target, it samples C/BE[3:0]#.
Even Parity: The 82C881 calculates PAR for both the address and data phases
of PCI cycles. PAR is valid one PCI clock after the associated address or data
phase, but may or may not be valid for subsequent clocks. It is calculated based
on 36 bits - AD[31:0] plus C/BE[3:0]#. "Even" parity means that the sum of the 36
bit values plus PAR is always an even number, even if one or more bits of
C/BE[3:0]# indicate invalid data.
Cycle Frame: This signal is driven by the current PCI bus master to indicate the
beginning and duration of an access. The master asserts FRAME# at the
beginning of a bus cycle, sustains the assertion during data transfers, and then
negates FRAME# in the final data phase.
FRAME# is an input when the 82C881 is the target and an output when it is the
initiator.
FRAME# is tristated from the leading edge of RESET# and remains tristated until
driven as either a master or slave by the 82C881.
912-2000-031
Revision: 1.0
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