82C881 Datasheet, PDF (20/46 Pages) List of Unclassifed Manufacturers – FireLink 1394 OHCI Link Controller

FireLink 1394 OHCI
82C881
Following is the list of main functions performed by this block.
• Chooses packet types for transmitting to the PHY, corresponding to whether the state of this period is isochronous or
asynchronous.
• Adds header CRC and data CRC information to the packet to be transmitted. The CRC is calculated per clause 6.4,
page 171 of IEEE 1394-1995.
• Converts 32-bit parallel data into two, four, or eight bits of serial data depending on the speed of transmission.
• Decodes the different fields of the status transfer from the PHY.
• Sends appropriate patterns to the PHY on the PHYLREQ line.
• Generates PHYLPS signal to the PHY.
• Implements the out-bound single-phase retry logic.
4.2 Serial EEPROM Interface
This interface is capable of performing reads as well as writes onto a 256 byte two wire Serial EEPROM (AT24C01 or similar).
Information like GUID, Subsystem ID, Subsystem Vendor ID, some PCI configuration register values and a few OHCI register
values can be stored in the Serial PROM. These values will be loaded from the Serial EEPROM after a power on reset if the
82C881 detects its presence through a pull up on the SDA pin. If the EEPROM is not present (SDA sensed LOW after reset),
default values are loaded instead.
PCICFG registers initialized from EEPROM data:
1. Subsystem ID
2. Subsystem vendor ID
3. PCI maximum latency, PCI minimum grant
OHCI registers initialized from EEPROM data:
1. Link enhancements control register
2. Host Control register
3. GUID
4.2.1 Read Operations from the Serial EEPROM
Data from the serial EEPROM can be read through a PCI read cycle at any time other than in the power-on read phase. The
sequence for reading data out of the EEPROM is as follows
1. Write the desired byte count (up to 8) of the READ operation in PCICFG 53h[6:3] and the eight bit start address on
PCICFG 50h[7:0].
2. Set PCICFG 53h[0]=1 to start the EEPROM read state machine.
3. When PCICFG 53h[0] reads back 0, the operation is complete and and PCICFG 53h[2] contains the operation status: 0
for OK, 1 for ERROR.
4. If there is no error, data can be read from PCICFG 54h[31:0] (EEPROM_DATA1), and also PCICFG 58h[31:0]
(EEPROM_DATA2) if the read byte count is greater than 4.
If an error occurs during a power-on reset EEPROM configuration read, the default values are loaded.
4.2.2 Write operations to the Serial EEPROM
Data can be written to the serial EEPROM through PCI write cycles after the power-on read is completed.
1. Write the data in registers EEPROM_DATA1 and EEPROM_DATA2.
2. Write the byte count in PCICFG 53h[6:3].
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