82C881 Datasheet, PDF (15/46 Pages) List of Unclassifed Manufacturers – FireLink 1394 OHCI Link Controller

FireLink 1394 OHCI
®
82C881
4.0 Functional Description
The OPTi 82C881 1394 OHCI Link Controller sits between the PCI bus as host bus on one side, and the P1394-compliant
PHY on the other side. On the host bus side, it interfaces to a 33MHz, 32-bit PCI bus.
The 82C881 can initiate read/write transactions on the PCI bus. It supports burst accesses for both read and write transactions
with zero wait states.
The logic core supports three register spaces:
• PCI Configuration register set, mapped through standard PCI configuration cycles
• OHCI register set, mapped through either memory or I/O space
• FIFO Configuration register set, also mapped through either memory or I/O space.
When acting as a target of the PCI bus, the 82C881 supports byte aligned accesses for PCI Configuration Registers and
quadlet (32-bit word) aligned accesses for the OHCI and FIFO Configuration registers.
Any packet coming from the 1394 serial bus is processed by the PHY, which then moves the data to the 82C881 per the 1394
packet format specification. According to the speed code received, data from data lines is read and converted to 32 bit
quadlets. The received packet is passed through several checks such as header and data CRCs, packet type, and packet
addressing with respect to physical and asynchronous request filters. The 82C881 converts the incoming packets in 1394
format to OHCI format and puts them on the PCI bus by through a write operation.
When a packet has to be transmitted, the 82C881 gets the required data from the host Memory through the PCI bus in OHCI
format by a read operation through the host interface. The 82C881 converts the data to 1394 packet format and passes it on to
the PHY, which in turn puts it out on the 1394 serial bus. For transmission, a specific packet is chosen based on its phase,
isochronous or asynchronous, and priority among asynchronous packets as defined in 1394 OHCI specification1.0. Depending
on the packet to be sent, the 82C881 sends different requests to the PHY through LReq patterns. It transmits the packet when
the PHY wins the arbitration. Data will be transmitted on the data lines as appropriate for the PHY speed.
If the 82C881 is the root node, cycle start packets are formed and sent out at every cycle sync event. Bus reset packets are
written into the Receive FIFO of the 82C881 whenever there is a bus reset indication.
Software has to program the necessary configuration registers to enable the software context. Once the context is active, the
system is ready to receive and transmit packets.
The 82C881 has an interface to an external serial EEPROM. This memory device should contain the GUID of the 82C881 and
may contain initialization information. The GUID is read only once after host power reset by an autonomous load operation
from the EEPROM, if present, by the 82C881.
4.1 Functional Block Description
A logic block diagram is provided on the following page. The key sub elements shown in the diagram are described below.
4.1.1 PCI Interface
The PCI Interface block is the interface to the PCI bus; it performs bus master functions and can act as a target as well. As a
target, it responds to I/O and Memory transactions. Lock transactions are not supported.
Target and master aborts occurring during a transaction are reported to the DMA control block. The PCI interface can perform
burst transfers both as a target and as a master.
Data Parity checking and reporting at the PCI bus interface is according to the PCI Local Bus Specifications 2.1. In case of a
data parity error during a transaction initiated by the 82C881, the transaction is terminated normally and error is reported to the
DMA control block. As a target, if an address parity error is detected, a target abort is generated.
PCI Power Management and PCI CLKRUN# functionality are supported as described elsewhere in this document.
912-2000-031
Revision: 1.0
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