82C881 Datasheet, PDF (13/46 Pages) List of Unclassifed Manufacturers – FireLink 1394 OHCI Link Controller

FireLink 1394 OHCI
82C881
Signal Name
Pin
No.
IDSEL
29
PERR#
49
SERR#
51
REQ#
15
GNT#
14
CLKRUN#
7
INTA#
8
Pin
Type
I
I/O
I
O
I
I/O
I/O
Signal Description
Initialization Device Select: This signal is the "chip select" during configuration
read and write cycles. IDSEL is sampled by the 82C881 during the address
phase of a cycle. If IDSEL is found to be active and the bus command is a
configuration read or write, the 82C881 claims the cycle with DEVSEL#.
Parity Error: The 82C8681 uses this line to report data parity errors during any
PCI cycle except a Special Cycle.
System Error: The 82C881 uses this line to report address parity errors and data
parity errors on the Special Cycle command, or any other system error where the
result will be catastrophic.
Bus Request: REQ# is asserted by the 82C881 to request ownership of the PCI
bus.
Bus Grant: GNT# is sampled by the 82C881 for an active low assertion, which
indicates that it has been granted use of the PCI bus.
Clock Run: The CLKRUN# function is available on this pin and can be used to
reduce chip power consumption during idle periods. It is an I/O sustained tristate
signal and follows the PCI 2.1 defined protocol.
Interrupt: The INTA# pin function is available on this pin and can be used to
reduce chip power consumption during idle periods. It is an I/O sustained tristate
signal and follows the PCI 2.1 defined protocol.
3.4.2 PHY-Link Interface Signal Set
Signal Name
Pin
No.
Pin Signal Description
Type
PHYLREQ
97
PHYCTL[1:0]
92, 93
PHY
DATA[7:0]
PHYSCLK
Refer to
Pin
Diagram
95
PHYLPS
99
PHYLINKON
98
ISOLATED#
79
O
Link Request: This signal is used by the 82C881 to request access to the serial
bus and to read or write PHY registers.
I/O Link-PHY Control Bus: These two signals are used by both the Link and PHY
devices to transfer control information to and from each other.
I/O Link-PHY Data Bus: Data is transferred between the Link and PHY devices over
DATA[7:0].
I
System Clock: This clock is generated by the PHY to the Link when PHYLPS is
high, and is used to synchronize data transfer between the Link and PHY. Its
specified frequency is 49.152MHz.
O
Link Power Status: Indicates to the PHY whether or not link activity is required.
I/O Link On: Wakeup indication.
I
“Isolated” Indicator from PHY: The PHY sets this signal active to indicate that it
has electrically isolated itself from the 82C881 Link Controller.
912-2000-031
Revision: 1.0
®
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